Arithmetic transforms for verifying compositions of sequential datapaths

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 348-353

  Radecka, K ^a   Zilic, Z ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS;

DISTRIBUTED ARITHMETIC (DA) CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 0035188752     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. The formal verification of pipelined double-precision IEEE floating-point multiplier
2. Power scalable processing using distributed arithmetic
3. A complex multiplier with low logic depth
4. Verification of arithmetic functions with binary moment diagrams
5. The K*BMD: A verification data structure
6. Efficient construction of binary moment diagrams for verification of arithmetic circuits
7. Assured VLSI design with formal verification
8. Using arithmetic transform for verification of datapaths via error modelling
9. Polynomial methods for allocating complex components
10. Applications of distributed arithmetic to digital signal processing: A tutorial review