On the verification of sequential equivalence

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 6, 2003, Pages 686-697

  Jiang, Jie Hong R ^a   Brayton, Robert K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Binary decision diagram (BDD); Equivalence checking; Formal verification; Sequential machines; Symbolic techniques

Indexed keywords

COMPUTATIONAL METHODS; MICROPROCESSOR CHIPS; PROBLEM SOLVING; SEQUENTIAL MACHINES;

BINARY DECISION DIAGRAMS (BDD);

COMPUTER AIDED DESIGN;

EID: 0038718553     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.811446     Document Type: Conference Paper

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