Automatic formal verification of DSP software

Proceedings-Design Automation Conference

Volumn , Issue , 2000, Pages 130-135

  Currie, David W ^a   Hu, Alan J ^b   Rajan, Sreeranga ^c   Fujita, Masahiro ^c,d  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^c FUJITSU LABORATORIES OF AMERICA   (United States)

^d UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; PROGRAM DEBUGGING; SUBROUTINES;

ASSEMBLY LANGUAGE ROUTINES; AUTOMATIC FORMAL VERIFICATION; CONTROL FLOW ANALYSIS; STANFORD VALIDITY CHECKER; SYMBOLIC SIMULATION;

COMPUTER SOFTWARE SELECTION AND EVALUATION;

EID: 0033684556     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2000.855291     Document Type: Article

References (10)

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