Polynomial circuit models for component matching in high-level synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 6, 2001, Pages 783-800

  Smith, James ^b   De Micheli, Giovanni ^a,b  

^a IEEE

^b STANFORD UNIVERSITY   (United States)

Author keywords

Binary decision diagrams (BDDs); High level synthesis; Polynomials

Indexed keywords

COMBINATORIAL CIRCUITS; DIGITAL LIBRARIES; ERROR ANALYSIS; IIR FILTERS; MATHEMATICAL MODELS; SEQUENTIAL CIRCUITS;

BINARY DECISION DIAGRAMS (BDD); POLYNOMIAL CIRCUIT MODELS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035708531     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.974892     Document Type: Article

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11. Implicit manipulation of polynomials using zero-suppressed BDDs