A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 770-775

  Satish Kumar, Y ^a   Li, Jun ^b   Talarico, Claudio ^a   Wang, Janet ^a  

^a UNIVERSITY OF ARIZONA   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT TIMING; GATE DELAY; MULTIPLE INPUT SWITCHING; ORTHOGONAL POLYNOMIAL;

CIRCUIT THEORY; ERROR ANALYSIS; POLYNOMIALS; PROBABILITY; STATISTICAL METHODS;

NANOTECHNOLOGY;

EID: 33646939014     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.31     Document Type: Conference Paper

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