메뉴 건너뛰기




Volumn II, Issue , 2005, Pages 1324-1329

An O(bn2) time algorithm for optimal buffer insertion with b buffer types

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATION; COMPUTATIONAL METHODS; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

EID: 33646902675     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.63     Document Type: Conference Paper
Times cited : (8)

References (15)
  • 1
    • 0030697661 scopus 로고    scopus 로고
    • Wire segmenting for improved buffer insertion
    • C. Alpert and A. Devgan. Wire segmenting for improved buffer insertion. In DAC, pages 588-593, 1997.
    • (1997) DAC , pp. 588-593
    • Alpert, C.1    Devgan, A.2
  • 2
    • 0031619501 scopus 로고    scopus 로고
    • Buffer insertion for noise and delay optimization
    • C. J. Alpert, A. Devgan, and S. T. Quay. Buffer insertion for noise and delay optimization. In DAC, pages 362-367, 1998.
    • (1998) DAC , pp. 362-367
    • Alpert, C.J.1    Devgan, A.2    Quay, S.T.3
  • 4
    • 49649136358 scopus 로고
    • An efficient algorithm for determining the convex hull of a fiite planar set
    • R. L. Graham. An efficient algorithm for determining the convex hull of a fiite planar set. Information Processing Letters, 1:132-133, 1972.
    • (1972) Information Processing Letters , vol.1 , pp. 132-133
    • Graham, R.L.1
  • 5
    • 0036374274 scopus 로고    scopus 로고
    • Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages
    • M. Hrkic and J. Lillis. Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. In ISPD,pages 98-103,2002.
    • (2002) ISPD , pp. 98-103
    • Hrkic, M.1    Lillis, J.2
  • 6
    • 0036048606 scopus 로고    scopus 로고
    • S-tree: A technique for buffered routing tree synthesis
    • M. Hrkic and J. Lillis. S-tree: a technique for buffered routing tree synthesis. In DAC, pages 578-583,2002.
    • (2002) DAC , pp. 578-583
    • Hrkic, M.1    Lillis, J.2
  • 7
    • 0030110490 scopus 로고    scopus 로고
    • Optimal wire sizing and buffer insertion for low power and a generalized delay model
    • J. Lillis, C. K. Cheng, and T.-T. Y. Lin. Optimal wire sizing and buffer insertion for low power and a generalized delay model. WEE Trans. Solid-state Circuits, 31(3):437-447, 1996.
    • (1996) WEE Trans. Solid-state Circuits , vol.31 , Issue.3 , pp. 437-447
    • Lillis, J.1    Cheng, C.K.2    Lin, T.-T.Y.3
  • 8
    • 0029712263 scopus 로고    scopus 로고
    • New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
    • J. Lillis, C.-K. Cheng, T.-T. Y. Lin, and C.-Y. Ho. New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing. In DAC, pages 395-400,1996.
    • (1996) DAC , pp. 395-400
    • Lillis, J.1    Cheng, C.-K.2    Lin, T.-T.Y.3    Ho, C.-Y.4
  • 9
    • 0030410359 scopus 로고    scopus 로고
    • Buffered steiner tree construction with wire sizing for interconnect layout optimization
    • T. Okamoto and J. Cong. Buffered steiner tree construction with wire sizing for interconnect layout optimization. In ICCAD, pages 44-49, 1996.
    • (1996) ICCAD , pp. 44-49
    • Okamoto, T.1    Cong, J.2
  • 11
    • 33746798902 scopus 로고    scopus 로고
    • A fast algorithm for opitimal buffer insertion
    • to appear
    • W. Shi and Z. Li. A fast algorithm for opitimal buffer insertion. IEEE Trans. CAD, to appear.
    • IEEE Trans. CAD
    • Shi, W.1    Li, Z.2
  • 12
    • 0041633712 scopus 로고    scopus 로고
    • An O(nlogn) time algorithm for optimal buffer insertion
    • W. Shi and Z. Li. An O(nlogn) time algorithm for optimal buffer insertion. In DAC, pages 580-585,2003.
    • (2003) DAC , pp. 580-585
    • Shi, W.1    Li, Z.2
  • 13
    • 2442496236 scopus 로고    scopus 로고
    • Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
    • W. Shi, Z. Li, and C. J. Alpert. Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. In ASPDAC, pages 609414,2004.
    • (2004) ASPDAC , pp. 609414
    • Shi, W.1    Li, Z.2    Alpert, C.J.3
  • 14
    • 0025594311 scopus 로고
    • Buffer placement in distributed RC-tree network for minimal elmore delay
    • L.P.P.P. van Ginneken, Buffer placement in distributed RC-tree network for minimal elmore delay. In ISCAS, pages 865-868, 1990.
    • (1990) ISCAS , pp. 865-868
    • Van Ginneken, L.P.P.P.1
  • 15
    • 0034229328 scopus 로고    scopus 로고
    • Simultaneous routing and buffer insertion with restrictions on buffer locations
    • H. Zhou, D. F. Wong, I. M. Liu, and A. Aziz. Simultaneous routing and buffer insertion with restrictions on buffer locations. IEEE Trans. CAD, 19(7):819-824, 2000.
    • (2000) IEEE Trans. CAD , vol.19 , Issue.7 , pp. 819-824
    • Zhou, H.1    Wong, D.F.2    Liu, I.M.3    Aziz, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.