Yield driven gate sizing for coupling-noise reduction under uncertainty

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 192-197

  Sinha, Debjit ^a   Zhou, Hai ^a  

^a Northwestern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; GATES (TRANSISTOR);

COUPLING NOISE; FIXPOINT COMPUTATIONS; GATE SIZING; MANUFACTURING PROCESS; PROBABILISTIC MODELS; PROCESS VARIATION; REDUCTION PROBLEM; TRADITIONAL APPROACHES;

NOISE ABATEMENT;

EID: 33646735266     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120803     Document Type: Conference Paper

References (16)

1. S. I. Association, "National technology roadmap for semiconductors," 1999.
2. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitectures," in Proc. of the Design Automation Conf, 2003, pp. 338-342.
3. S. Nassif, "Modeling and analysis of manufacturing variations," in Proc. Custom Integrated Circuits Conf, 2001.
4. C. Visweswariah, "Death, taxes and failing chips," in Proc. of the Design Automation Conf., 2003, pp. 343-347
5. T. Xiao and M. Marek-Sadowska, "Crosstalk reduction by transistor sizing," in Proc. Asian and South Pacific Design Automation Conference, 1999, pp. 137-140.
6. M. Hashimoto, M. Takahashi, and H. Onodera, "Crosstalk noise optimisation by post-layout transistor sizing," in International Symposium on Physical Design, 2002, pp. 126-130.
7. M. R. Becer, D. Blauuw, 1. Algor, R. Panda, C. Oh, V Zolotov, and I. n. Hajj, "Post-route gate sizing for crosstalk noise reduction," in Proc. of the Design Automation Conf, 2003, pp. 954-957.
8. D. Sinha, H. Zhou, and C. Chu, "Optimal gate sizing for coupling noise reduction," in International Symposium on Physical Design, 2004, pp. 176-181.
9. D. Sinha and H. Zhou, "Gate sizing for crosstalk reduction under timing constraints by Lagrangian Relaxation," in Proc. Intl. Conf. on Compuler-Aided Design, 2004.
10. H, Zhou, 'Timing analysis with crosstalk is a fixpoint on a complete lattice," in IEEE Transactions on .Computer-Aided Design, September 2003, pp. 1261-1269.
11. F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinatorial benchmark circuits," in Proc. Intl. Symposium on Circuits and Systems, 1985, pp. 695-698.
12. G. Grimmett and D. Stirzaker, Probability and random processes. Oxford University Press, 2002.
13. D. Gries and F. B. Schneider, A logical approach to discrete math. Springer-Verlag New York, Inc., 1994.
14. B. A. Davey and H. A. Priestley, Introduction to lattices and order. Cambridge, 1990.
15. P. Cousot and R. Cousot, "Abstract interpretation: A unified lattice model for static analysis of programs by construction or approximation of fix-points," in ACM Symposium on Principles of Programming Languages, Los Angeles, CA, Jan. 1977, pp. 238-252.
16. J. Cong, D. Z. Pang, and P. V. Srinivas, "Improved crosstalk modeling for noise constrained interconnect optimization," in ACM Intl. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2000.