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Volumn , Issue , 2003, Pages 954-957

Post-route gate sizing for crosstalk noise reduction

Author keywords

Crosstalk noise repair; Gate sizing

Indexed keywords

ALGORITHMS; CROSSTALK; ELECTRIC NETWORK ANALYSIS; HEURISTIC METHODS; NOISE ABATEMENT; SPURIOUS SIGNAL NOISE;

EID: 0043136427     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/776067.776071     Document Type: Conference Paper
Times cited : (9)

References (6)
  • 3
    • 0035188668 scopus 로고    scopus 로고
    • Gate sizing to eliminate crosstalk induced timing violation
    • T. Xiao and M. Marek-Sadowska. Gate sizing to eliminate crosstalk induced timing violation. In Proceedings of ICCD, pages 186-191, 2001.
    • (2001) Proceedings of ICCD , pp. 186-191
    • Xiao, T.1    Marek-Sadowska, M.2
  • 4
    • 0036375783 scopus 로고    scopus 로고
    • Crosstalk noise optimization by post-layout transistor sizing
    • M. Hashimoto, M. Takahashi, and H. Onodera. Crosstalk noise optimization by post-layout transistor sizing. In Proceedings of ISPD, pages 126-130, 2002.
    • (2002) Proceedings of ISPD , pp. 126-130
    • Hashimoto, M.1    Takahashi, M.2    Onodera, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.