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Volumn , Issue , 2004, Pages 14-19

Gate sizing for crosstalk reduction under timing constraints by Lagrangian Relaxation

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK REDUCTION; GATE SIZING; LAGRANGIAN RELAXATION; TIMING CONSTRAINTS;

EID: 16244413958     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (17)

References (12)
  • 2
    • 0035188668 scopus 로고    scopus 로고
    • Gate sizing to eliminate crosstalk induced timing violation
    • T. Xiao and M. Marek-Sadowska, "Gate sizing to eliminate crosstalk induced timing violation," in ICCD, 2001.
    • (2001) ICCD
    • Xiao, T.1    Marek-Sadowska, M.2
  • 3
    • 0036375783 scopus 로고    scopus 로고
    • Crosstalk noise optimization by post-layout transistor sizing
    • M. Hashimoto, M. Takahashi, and H. Onodera, "Crosstalk noise optimization by post-layout transistor sizing," in ISPD, 2002.
    • (2002) ISPD
    • Hashimoto, M.1    Takahashi, M.2    Onodera, H.3
  • 7
    • 0022031091 scopus 로고
    • An applications oriented guide to lagrangian relaxation
    • March/April
    • M. L. Fisher, "An applications oriented guide to lagrangian relaxation," in Interfaces, vol 15, March/April 1985, pp. 10-21.
    • (1985) Interfaces , vol.15 , pp. 10-21
    • Fisher, M.L.1
  • 9
    • 0034259185 scopus 로고    scopus 로고
    • Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
    • September 2000
    • I. H. Jiang, Y. Vhang, and J. Jao, "Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing," in IEEE Transactions on Computer-Aided Design, September 2000, 2000, pp. 999-1010.
    • (2000) IEEE Transactions on Computer-aided Design , pp. 999-1010
    • Jiang, I.H.1    Vhang, Y.2    Jao, J.3
  • 10
    • 2942689381 scopus 로고    scopus 로고
    • Optimal gate sizing for coupling noise reduction
    • D. Sinha, H. Zhou, and C. Chu, "Optimal gate sizing for coupling noise reduction," in ISPD, 2004.
    • (2004) ISPD
    • Sinha, D.1    Zhou, H.2    Chu, C.3
  • 11
    • 0002609165 scopus 로고
    • A neutral netlist of 10 combinatorial benchmark circuits
    • F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinatorial benchmark circuits," in ISCAS, 1985, pp. 695-698.
    • (1985) ISCAS , pp. 695-698
    • Brglez, F.1    Fujiwara, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.