A low cost, multithreaded processing-in-memory system

ACM International Conference Proceeding Series

Volumn 68, Issue , 2004, Pages 16-22

  Brockman, Jay B ^a   Thoziyoor, Shyamkumar ^a   Kuntz, Shannon K ^a   Kogge, Peter M ^a  

^a University of Notre Dame   (United States)

Author keywords

PIM; processing in memory

Indexed keywords

COST EFFICIENCY; LOW COSTS; LOW LATENCY; MEMORY SYSTEMS; MULTITHREADED; MULTITHREADED PROCESSORS; PERFORMANCE TRADE-OFF; PROCESSING-IN-MEMORY; PROCESSING-IN-MEMORY SYSTEMS; PROCESSOR DESIGN; PROTOTYPE CHIP;

COMPUTER ARCHITECTURE; COMPUTERS; COSTS; DYNAMIC RANDOM ACCESS STORAGE; MICROPROCESSOR CHIPS; NANOTECHNOLOGY;

COST BENEFIT ANALYSIS;

EID: 77954447075     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1054943.1054946     Document Type: Conference Paper

References (37)

1. T. Takahashi et. al. A multi-gigabit DRAM technology with 6F2 open-bit-line cell distributed over-driven sensing and stacked-flash fuse. In International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2002. IEEE, IEEE.
2. ARM. ARM thumb family, www.arm.com, 2003.
3. J. Barnes and P. Hut. A hierarchical O(N logN) force-calculation algorithm. Nature, 324(4):446-449, Dec. 1986.
4. J. B. Brockman. PIM lite architecture and assembly language manual. Technical report, University of Notre Dame CSE Dept., July 2003.
5. J. B. Brockman. Programming PIM lite. Technical report, University of Notre Dame CSE Dept., July 2003.
6. J. B. Brockman, P. M. Kogge, V. W. Freeh, S. K. Kuntz, and T. L. Sterling. Microservers: A new memory semantics for massively parallel computing. In Conference Proceedings of the 1999 International Conference on Supercomputing, pages 454-463, Rhodes, Greece, June 20-25, 1999. ACM SIGARCH.
7. D. E. Culler, S. C. Goldstein, K. E. Schauser, and T. Von Eicken. TAM - A compiler controlled Threaded Abstract Machine. Journal of Parallel and Distributed Computing, 18(3):347-370, July 1993.
8. D. E. Culler, A. Sah, K. E. Schauser, T. von Eicken, and J. Wawrzynek. Fine-grain parallelism with minimal hardware support: A compiler-controlled threaded abstract machine. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 164-175, Apr. 1991.
9. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, Published in Vol.26, No.4. Apr.1991. Also as Tech report UCB-CSD-90-594, University of California Berkeley, Department of Computer Science.
10. W. J. Dally et. al. The message driven processor: An integrated multicomputer processing element. In International Conference on Computer Design, VLSI in Computers and Processors, pages 416-419, Los Alamitos, CA, Oct. 1992. IEEE Computer Society Press.
11. W. J. Dally et. al. The message-driven processor. IEEE Micro, pages 23-39, Apr. 1992.
12. J. Draper et. al. The architecture of the DIVA processing-in-memory chip. In ACM International Conference on Supercomputing (ICS'02), June 2002.
13. B. Fraguela, P. Feautrier, J. Renau, D. Padua, and J. Torrellas. Programming the flexram parallel intelligent memory system. In International Symposium on Principles and Practice of Parallel Programming, June 2003.
14. IBM. The powerPC 440 core. Technical report, IBM Microelectronics Division, Research Triangle Park, NC, Sept. 1999.
15. IBM. IBM SA-27E Embedded DRAM Macro Datasheet, Apr. 2002.
16. IBM. Embedded Memory Selection Guide. http://www-3.ibm.com/chips/ products/asics/products/ememory.html, Mar. 2003.
17. K. Iobst, M. Gokhale, and B. Holmes. Processing in memory: The Terasys massively parellel PIM array. IEEE Computer, 28(4):23-??, Apr. 1995.
18. R. M. Jessani and M. Putrino. Comparison of single and dual pass multiply add fused floating point units. IEEE Transactions on Computers, 47(9):927-937, 1998.
19. T. Kirihata et. al. A 113 mm2 600 mb/s/pin 512 mb DDR2 SDRAM with vertically-folded bitline architecture. In International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2002. IEEE, IEEE.
20. G. Kirsch. Active memory device delivers massive parallelism. In Microprocessor Forum, San Jose, CA, Oct. 2002.
21. G. Konstadinidis et. al. Implementation of a third-generation 1.1GHz 64b microprocessor. In International Solid-State Circuits Conference (ISSCC), page 338, San Francisco, CA, Feb. 2002. IEEE, IEEE.
22. C. Kozyrakis, J. Gebis, D. Martin, S. Williams, I. Mavroidis, S. Pope, D. Jones, and D. Patterson. Vector IRAM: A media-enhanced vector processor with embedded DRAM. In IEEE, editor, Hot Chips 12: Stanford University, Stanford, California, August 13-15, 2000, pages ??-??, 1109 Spring Street, Suite 300, Silver Spring, MD 20910, USA, 2000. IEEE Computer Society Press.
23. G. Lipovski and C. Yu. The dynamic associative access memory chip and its application to SIMD processing and full-text database retrieval. In IEEE International Workshop on Memory Technology, Design and Testing, pages 24-33, San Jose, CA, Aug. 1999. IEEE, IEEE Computer Society.
24. MIPS. MIPS64 5K family, www.mips.com, 2003.
25. S. D. Naffziger and G. Hammond. The implementation of the next-generation 64 b itanium microprocessor. In International Solid-State Circuits Conference (ISSCC), page 344, San Francisco, CA, Feb. 2002. IEEE, IEEE.
26. R. S. Nikhil and Arvind. Can dataflow subsume von Neumann computing? In Proceedings of the 16th Annual International Symposium on Computer Architecture, pages 262-272, June 1989.
27. M. D. Noakes, D. A. Wallach, and W. J. Dally. The J-machine multicomputer: An architectural evaluation. In L. Bic, editor, Proceedings of the 20th Annual International Symposium on Computer Architecture, pages 224-236, San Diego, CA, May 1993. IEEE Computer Society Press.
28. M. Oskin, F. Chong, and T. Sherwood. Active pages: A computation model for intelligent memory. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA-98), volume 26,3 of ACM Computer Architecture News, pages 192-203, New York, June 27-July 1 1998. ACM Press.
29. G. M. Papadopoulos and D. E. Culler. Monsoon: An explicit token-store architecture. In 17th International Symposium on Computer Architecture, number 18(2) in ACM SIGARCH Computer Architecture News, pages 82-91, Seattle, Washington, May 28-31, June 1990.
30. R. P. Preston et. al. Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading. In International Solid-State Circuits Conference (ISSCC), page 334, San Francisco, CA, Feb. 2002. IEEE, IEEE.
31. A. Saulsbury, F. Pong, and A. Nowatzyk. Missing the memory wall: The case for processor/memory integration. In 23rd Annual International Symposium on Computer Architecture (23rd ISCA'96), Computer Architecture News, pages 90-101. ACM SIGARCH, May 1996.
32. Semiconductor Industries Association. International technology roadmap for semiconductors. Technical report, 2001.
33. T. Sterling and L. Bergman. A design analysis of a hybrid technology multithreaded architecture for petaflops scale computation. In Conference Proceedings of the 1999 International Conference on Supercomputing, pages 286-293, Rhodes, Greece, June 20-25, 1999. ACM SIGARCH.
34. T. Sterling and H. Zima. Gilgamesh: A multithreaded processor-in-memory architecture for petaflops computing. In Supercomputing: High-Performance Networking and Computing, Nov. 2002.
35. S. Thoziyoor. PIM lite: VLSI prototype of a multithreaded processor-in-memory chip. M.s. thesis, University of Notre Dame, Apr. 2004.
36. T. von Eicken, D. E. Culler, S. C. Goldstein, and K. E. Schauser. Active messages: a mechanism for integrated communication and computation. In Proceedings the 19th Annual International Symposium on Computer Architecture, pages 256-266, Gold Coast, Australia, May 1992.
37. H. Yoon et. al. A 4 gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture. In International Solid-State Circuits Conference (ISSCC), pages 378-79, San Francisco, CA, Feb. 2002. IEEE, IEEE.