Post-layout transistor sizing for power reduction in cell-base design

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E84-A, Issue 11, 2001, Pages 2769-2777

  Hashimoto, Masanori ^a   Onodera, Hidetoshi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

Cell base design; Gate sizing; Low power design; Post layout optimization; Transistor sizing

Indexed keywords

ALGORITHMS; CALCULATIONS; EVALUATION; INTEGRATED CIRCUIT TESTING; INTERPOLATION; ITERATIVE METHODS; MATHEMATICAL MODELS; MOSFET DEVICES; OPTIMIZATION; POWER CONTROL; THRESHOLD VOLTAGE;

CELL-BASE DESIGN; POST-LAYOUT OPTIMIZATION; POWER REDUCTION; TRANSISTOR SIZING METHOD;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035518397     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (18)

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