An AND-type match-line scheme for high-performance energy-efficient content addressable memories

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 5, 2006, Pages 1108-1119

  Li, Hung Yu ^a,b,c   Chen, Chia Cheng ^a,b,c   Wang, Jinn Shyan ^a,b   Yeh, Chingwei ^b  

^a IEEE   (Taiwan)

^b NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^c FARADAY TECHNOLOGY CORPORATION   (Taiwan)

Author keywords

Content addressable memory (CAM); Low power; Match line scheme

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA ACQUISITION; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS;

CONTENT-ADDRESSABLE MEMORY (CAM); LOW POWER; MATCH LINE SCHEME;

DATA STORAGE EQUIPMENT;

EID: 33646390670     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.872719     Document Type: Conference Paper

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