Analysis and design of high-speed and low-power CMOS PLAs

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 8, 2001, Pages 1250-1262

  Wang, Jinn Shyan ^a,b   Chang, Ching Rong ^a,b   Yeh, Chingwei ^b  

^a IEEE   (Taiwan)

^b NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

High speed; Low power; PLA; Pseudofootless dynamic CMSOS logic circuit

Indexed keywords

PROGRAMMABLE LOGIC ARRAYS (PLA);

ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; WAVEFORM ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 0035429464     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.938375     Document Type: Article

References (9)

1. Design methodology for a 1.0 GHz microprocessor
2. ARM7TDMI power consumption
3. PLA design for single-clock CMOS
4. High speed CMOS POS PLA using pre-discharged OR array and charge sharing AND array
5. A low-power and high-speed dynamic PLA circuit configuration for single-clock CMOS