-
1
-
-
33747574386
-
"Analytical modeling and characterization of deep-submicrometer interconnect"
-
May
-
D. Sylvester and C. Hu, "Analytical modeling and characterization of deep-submicrometer interconnect," Proc. IEEE, vol. 89, no. 5, pp. 634-664, May 2001.
-
(2001)
Proc. IEEE
, vol.89
, Issue.5
, pp. 634-664
-
-
Sylvester, D.1
Hu, C.2
-
2
-
-
0346941038
-
"Future interconnect technologies and copper metallization"
-
Oct
-
X. W. Lin and D. Pramanik, "Future interconnect technologies and copper metallization," Solid State Technol., vol. 41, no. 10, pp. 63-79, Oct. 1998.
-
(1998)
Solid State Technol.
, vol.41
, Issue.10
, pp. 63-79
-
-
Lin, X.W.1
Pramanik, D.2
-
3
-
-
33646935598
-
"An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique"
-
J. C. Chen, B. W. McGaughy, D. Sylvester, and C. Hu, "An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique," in IEDM Tech. Dig., 1996, pp. 3.4.1-3.4.4.
-
(1996)
IEDM Tech. Dig.
-
-
Chen, J.C.1
McGaughy, B.W.2
Sylvester, D.3
Hu, C.4
-
4
-
-
25944470717
-
"Ultra low capacitance measurements in multilevel metallisation CMOS by using a built-in electron-meter"
-
B. Froment, F. Paillardet, M. Bely, J. Cluzel, E. Granger, M. Haond, and L. Dugoujon, "Ultra low capacitance measurements in multilevel metallisation CMOS by using a built-in electron-meter," in IEDM Tech. Dig., 1999, pp. 37.2.1-37.2.4.
-
(1999)
IEDM Tech. Dig.
-
-
Froment, B.1
Paillardet, F.2
Bely, M.3
Cluzel, J.4
Granger, E.5
Haond, M.6
Dugoujon, L.7
-
5
-
-
2442573874
-
"Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution"
-
May
-
T. Kunikiyo, T. Watanabe, T. Kanamoto, H. Asazato, M. Shirota, K. Eikyu, Y. Ajioka, H. Makino, K. Ishikawa, S. Iwade, and Y. Inoue, "Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution," IEEE Trans. Electron Devices, vol. 51, no. 5, pp. 726-735, May 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.5
, pp. 726-735
-
-
Kunikiyo, T.1
Watanabe, T.2
Kanamoto, T.3
Asazato, H.4
Shirota, M.5
Eikyu, K.6
Ajioka, Y.7
Makino, H.8
Ishikawa, K.9
Iwade, S.10
Inoue, Y.11
-
6
-
-
0242364173
-
"Measurements and extractions of parasitic capacitances in ULSI layouts"
-
Nov
-
A. Brambilla, P. Maffezzoni, L. Bortesi, and L. Vendrame, "Measurements and extractions of parasitic capacitances in ULSI layouts," IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2236-2247, Nov. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.11
, pp. 2236-2247
-
-
Brambilla, A.1
Maffezzoni, P.2
Bortesi, L.3
Vendrame, L.4
-
7
-
-
2442430553
-
"A novel simple CBCM method free from charge injection-induced errors"
-
May
-
Y. W. Chang, H. W. Chang, C. H. Hsieh, H. C. Lai, T. C. Lu, W. Ting, J. Ku, and C. Y. Lu, "A novel simple CBCM method free from charge injection-induced errors," IEEE Electron Device Lett., vol. 25, no. 5, pp. 262-264, May 2004.
-
(2004)
IEEE Electron Device Lett.
, vol.25
, Issue.5
, pp. 262-264
-
-
Chang, Y.W.1
Chang, H.W.2
Hsieh, C.H.3
Lai, H.C.4
Lu, T.C.5
Ting, W.6
Ku, J.7
Lu, C.Y.8
-
8
-
-
27644532654
-
"A novel CBCM method free from charge injection induced errors: Investigation into the impact of floating dummy-fills on interconnect capacitance"
-
Apr
-
Y. W. Chang, H. W. Chang, T. C. Lu, Y.-C. King, W. Ting, J. Ku, and C. Y. Lu, "A novel CBCM method free from charge injection induced errors: Investigation into the impact of floating dummy-fills on interconnect capacitance," in Proc. ICMTS, Apr. 2005, pp. 235-238.
-
(2005)
Proc. ICMTS
, pp. 235-238
-
-
Chang, Y.W.1
Chang, H.W.2
Lu, T.C.3
King, Y.-C.4
Ting, W.5
Ku, J.6
Lu, C.Y.7
-
9
-
-
33144455985
-
"Interconnect capacitance characterization using charge-injection-induced-error-free (CIEF) charge-based capacitance measurement (CBCM)"
-
Feb
-
Y. W. Chang, H. W. Chang, T. C. Lu, Y.-C. King, W. Ting, J. Ku, and C. Y. Lu, "Interconnect capacitance characterization using charge-injection-induced-error-free (CIEF) charge-based capacitance measurement (CBCM)," IEEE Trans. Semicond. Manuf., vol. 19, no. 1, pp. 50-56, Feb. 2006.
-
(2006)
IEEE Trans. Semicond. Manuf.
, vol.19
, Issue.1
, pp. 50-56
-
-
Chang, Y.W.1
Chang, H.W.2
Lu, T.C.3
King, Y.-C.4
Ting, W.5
Ku, J.6
Lu, C.Y.7
-
10
-
-
33646238737
-
"Charge-based capacitance measurements (CBCM) on MOS devices"
-
Mar
-
B. Sell, A. Avellan, and W. H. Krautschneider, "Charge-based capacitance measurements (CBCM) on MOS devices," IEEE Trans. Device Mater. Rel., vol. 2, no. 1, pp. 9-12, Mar. 2002.
-
(2002)
IEEE Trans. Device Mater. Rel.
, vol.2
, Issue.1
, pp. 9-12
-
-
Sell, B.1
Avellan, A.2
Krautschneider, W.H.3
-
11
-
-
0021477881
-
"Switch-induced error voltage on a switched capacitor"
-
Aug. SSC-19
-
B. J. Sheu and C. Hu, "Switch-induced error voltage on a switched capacitor," IEEE J. Solid-State Circuits, vol. SSC-19, no. 4, pp. 519-525, Aug. 1984.
-
(1984)
IEEE J. Solid-State Circuits
, Issue.4
, pp. 519-525
-
-
Sheu, B.J.1
Hu, C.2
-
12
-
-
85063615704
-
"An accurate "Decoupled C-V" Method for characterizing channel and overlap capacitances of miniaturized MOSFET"
-
J. C. Guo, C. C. H. Hsu, P. S. Lin, and S. S. Chung, "An accurate "Decoupled C-V" method for characterizing channel and overlap capacitances of miniaturized MOSFET," in VLSI Symp. Tech. Dig., 1993, pp. 256-260.
-
(1993)
VLSI Symp. Tech. Dig.
, pp. 256-260
-
-
Guo, J.C.1
Hsu, C.C.H.2
Lin, P.S.3
Chung, S.S.4
-
13
-
-
0021187981
-
"Electrical characterization of feature sizes and parasitic capacitances using a single test structure"
-
Jan. ED-31
-
P. Vitanov, U. Schwabe, and I. Eisele, "Electrical characterization of feature sizes and parasitic capacitances using a single test structure," IEEE Trans. Electron Devices, vol. ED-31, no. 1, pp. 96-100, Jan. 1984.
-
(1984)
IEEE Trans. Electron Devices
, Issue.1
, pp. 96-100
-
-
Vitanov, P.1
Schwabe, U.2
Eisele, I.3
-
14
-
-
0342637501
-
"Measurement of minimum-geometry MOS transistor capacitances"
-
Feb. ED-32
-
J. J. Paulos and D. A. Antoniadis, "Measurement of minimum-geometry MOS transistor capacitances," IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 357-363, Feb. 1985.
-
(1985)
IEEE Trans. Electron Devices
, Issue.2
, pp. 357-363
-
-
Paulos, J.J.1
Antoniadis, D.A.2
|