Measurements and Extractions of Parasitic Capacitances in ULSI Layouts

IEEE Transactions on Electron Devices

Volumn 50, Issue 11, 2003, Pages 2236-2247

  Brambilla, Angelo ^a   Maffezzoni, Paolo ^a   Bortesi, Luca ^b   Vendrame, Loris ^b  

^a POLITECNICO DI MILANO   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

Floating random walk (FRW); Interconnect characterization; Parasitic capacitance

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTER SOFTWARE; INTEGRATED CIRCUIT LAYOUT;

PARASITIC CAPACITANCES;

ULSI CIRCUITS;

EID: 0242364173     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.818150     Document Type: Article

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