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Volumn , Issue , 2005, Pages 235-238

A novel CBCM method free from charge injection induced errors: Investigation into the impact of floating dummy-fills on interconnect capacitance

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CROSSTALK; MICROPROCESSOR CHIPS;

EID: 27644532654     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (12)

References (12)
  • 1
    • 0346941038 scopus 로고    scopus 로고
    • Future interconnect technologies and copper metallization
    • Oct
    • X. W. Lin and D. Pramanik, ì Future Interconnect Technologies and Copper Metallization,î Solid State Technology, pp. 63-79, Oct 1998.
    • (1998) Solid State Technology , pp. 63-79
    • Lin, X.W.1    Pramanik, D.2
  • 2
    • 33747574386 scopus 로고    scopus 로고
    • Analytical modeling and characterization of deep-submicrometer inter- Connect,î
    • May
    • D. Sylvester and C. Hu, ì Analytical Modeling and Characterization of Deep-Submicrometer Inter- connect,î Proceedings of the IEEE, Vol. 89, No. 5, pp. 634-664, May 2001.
    • (2001) Proceedings of the IEEE , vol.89 , Issue.5 , pp. 634-664
    • Sylvester, D.1    Hu, C.2
  • 3
    • 0036565356 scopus 로고    scopus 로고
    • Characterization and modeling of oxide chemical-mechanical polishing using planarization length and pattern density concepts
    • May
    • D. O. Ouma, D. S. Boning, J. E. Chung, W. G. Easter, V. Saxena, S. Misra, and A. Crevasse, ì Characterization and modeling of oxide chemical-mechanical polishing using planarization length and pattern density concepts,î IEEE Trans. Semiconductor Manufacturing, Vol.15, pp. 232-244, May 2002
    • (2002) IEEE Trans. Semiconductor Manufacturing , vol.15 , pp. 232-244
    • Ouma, D.O.1    Boning, D.S.2    Chung, J.E.3    Easter, W.G.4    Saxena, V.5    Misra, S.6    Crevasse, A.7
  • 6
    • 84942123552 scopus 로고    scopus 로고
    • Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling
    • March
    • W. Lee, K. Lee, J. Park, T. Kim, Y. Park, and J. Kong, ì Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling,î Symp. on Quality Electronic Design, pp. 373-376, March 2003
    • (2003) Symp. on Quality Electronic Design , pp. 373-376
    • Lee, W.1    Lee, K.2    Park, J.3    Kim, T.4    Park, Y.5    Kong, J.6
  • 7
    • 33646935598 scopus 로고    scopus 로고
    • An on-chip, attofarad interconnect Charge-Based Capacitance Measurement (CBCM) Technique
    • J. C. Chen, B. W. McGaughy, D. Sylvester, and C. Hu, ì An On-Chip, Attofarad Interconnect Charge-Based Capacitance Measurement (CBCM) Technique,î IEDM 1996, pp. 3.4.1-3.4.4.
    • IEDM 1996
    • Chen, J.C.1    McGaughy, B.W.2    Sylvester, D.3    Hu, C.4
  • 8
    • 25944470717 scopus 로고    scopus 로고
    • Ultra low capacitance measurements in multilevel metallisation CMOS by using a built-in electron-meter
    • B. Froment, F. Paillardet, M. Bely, J. Cluzel, E. Granger, M. Haond, and L. Dugoujon, ì Ultra Low Capacitance Measurements in Multilevel Metallisation CMOS by Using a Built-in Electron-Meter,î IEDM 1999, pp. 37.2.1-37.2.4.
    • IEDM 1999
    • Froment, B.1    Paillardet, F.2    Bely, M.3    Cluzel, J.4    Granger, E.5    Haond, M.6    Dugoujon, L.7
  • 11
    • 0021477881 scopus 로고
    • Switch-induced error voltage on a switched capacitor
    • Aug
    • B. J. Sheu and C. Hu, ì Switch-Induced Error Voltage on a Switched Capacitor,î IEEE J. Solid-State Circuits, Vol. SC-19, No.4, pp. 519-525, Aug 1984.
    • (1984) IEEE J. Solid-state Circuits , vol.SC-19 , Issue.4 , pp. 519-525
    • Sheu, B.J.1    Hu, C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.