A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors

IEEE Transactions on Microwave Theory and Techniques

Volumn 54, Issue 4, 2006, Pages 1554-1559

  Sun, Kuo Jung ^a,b   Tsai, Zuo Min ^a,b   Lin, Kun You ^a,c,d   Wang, Huei ^a,b,d,e  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^c SUNPLUS TECHNOLOGY CO LTD   (Taiwan)

^d Phi Tau Phi ^*  (United States)

^e RF Product Center   (Taiwan)

Author keywords

CMOS; Low noise amplifier (LNA)

Indexed keywords

LOW-NOISE AMPLIFIER (LNA); NOISE OPTIMIZATION; SERIES RESISTANCES;

CMOS INTEGRATED CIRCUITS; ELECTRIC INDUCTORS; ELECTRIC RESISTANCE; GAIN CONTROL; NATURAL FREQUENCIES; OPTIMIZATION;

AMPLIFIERS (ELECTRONIC);

EID: 33645944377     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2006.871365     Document Type: Article

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