Gain controllable very low voltage (≤ 1 V) 8-9 GHz integrated CMOS LNA's

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2002, Pages 205-208

  Tsang, Tommy K K ^a   El Gamal, Mourad N ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DIPLEX TRANSMISSION; EDDY CURRENTS; ELECTRIC LOSSES; ELECTRIC REACTANCE MEASUREMENT; GAIN CONTROL; NATURAL FREQUENCIES; SPURIOUS SIGNAL NOISE; WIRELESS TELECOMMUNICATION SYSTEMS;

POWER GAIN;

CMOS INTEGRATED CIRCUITS;

EID: 0036309610     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. High frequency AC characteristics of 1.5 nm gate oxide MOSFETs
2. High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection
3. A very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications
4. A sub-1 V 4 GHz CMOS VCO, and a 12.5 GHz oscillator for low-voltage and high-frequency applications
5. A 7-GHz 1.8 dB (minimum) NF CMOS low noise amplifier
6. A CMOS VCO architecture suitable for sub-1 volt high-frequency (8.7510 GHz) RF applications
7. A fully integrated 1 V 5.8 GHz bipolar LNA
8. A new design approach for variable-gain low noise amplifiers
9. A 2 dB NF, fully differential, variable gain, 900 MHz CMOS LNA
10. Performance limits of planar and multi-layer integrated inductors
11. Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs