A 7-GHz 1.8-dB NF CMOS low-noise amplifier

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 7, 2002, Pages 852-856

  Fujimoto, Ryuichi ^a,b   Kojima, Kenji ^b   Otaka, Shoji ^b  

^a IEEE   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

Dual gate MOSFET; Intercept point; Low noise amplifier; Noise figure; Shielded pad; Si substitute

Indexed keywords

LOW-NOISE AMPLIFIERS (LNA);

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; MOSFET DEVICES; SPURIOUS SIGNAL NOISE; SUBSTRATES;

AMPLIFIERS (ELECTRONIC);

EID: 0036641211     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.1015682     Document Type: Article

References (10)

1. 0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation
2. 0.2-μm analog CMOS with very low noise figure at 2-GHz operation
3. A 1.5-V 1.5-GHz CMOS low-noise amplifier
4. A 2.7-V 900-MHz CMOS LNA and mixer
5. A 2.7-V CMOS broadband low-noise amplifier
6. A 1-GHz CMOS RF front-end IC for a direct-conversion wireless receiver
7. A 0.8-dB NF ESD-protected 9-mW CMOS LNA
8. Effect of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology
9. Applying the series feedback technique to LNA design
10. An efficient method for computer-aided noise analysis of linear amplifier networks