Test consideration for nanometer-scale CMOS circuits

IEEE Design and Test of Computers

Volumn 23, Issue 2, 2006, Pages 128-136

  Kaushik, Roy ^a   Mak, T M ^b   Cheng, Kwang Tim ^c  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT TESTING; STATISTICAL METHODS;

NANOMETER-SCALE; TEST CONSIDERATION; TEST TECHNOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 33645827136     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2006.52     Document Type: Article

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