Characterizing metastability

Proceedings - 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1996

Volumn , Issue , 1996, Pages 175-184

  Foley, C ^a  

^a TEKTRONIX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC;

FAILURE RATE; MEAN TIME BETWEEN FAILURES; METASTABILITIES; PRACTICAL MEASUREMENT TECHNIQUES; TIME CONSTANTS;

FAILURE ANALYSIS;

EID: 84883477673     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1996.494449     Document Type: Conference Paper

References (4)

1. Stoll, Peter A., "How to Avoid Synchronization Problems," VLSI Design, Nov/Dec 1982, pp 56-59.
2. Bolton, Martin, "A Guided Tour of 35 Years of Metastability Research," Professional Program Session Record 16, WESCON 87, Nov 1987, pp 16/4, Electronic Conventions Management, Los Angeles, CA 90045.
3. Dingman, Sean, "Are Your PLDs Metastable?" Application Note, 17 July 1992, Cypress Semiconductor Corp., 3901 North First Street, CA 95134.
4. Nootbaar, Keith, "Design, Testing, and Application of a Metastable-Hardened Flip-Flop," Professional Program Session Record 16, WESCON 87, Nov 1987, pp 16/2, Electronic Conventions Management, Los Angeles, CA 90045.