Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution

IEEE Transactions on Instrumentation and Measurement

Volumn 46, Issue 1, 1997, Pages 51-55

  Kalisz, Jozef ^a   Szplet, Ryszard ^a   Pasierbinski, Jerzy ^a   Poniecki, Andrzej ^a  

^a MILITARY UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC DELAY LINES; ENCODING (SYMBOLS); FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE STRUCTURES;

AMORPHOUS ANTIFUSE STRUCTURE; DIGITAL CODING; FIELD PROGRAMMABLE GATE ARRAY; TIME TO DIGITAL CONVERTER;

ELECTRIC CONVERTERS;

EID: 0031078640     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/19.552156     Document Type: Article

References (12)

1. P. S. Stephenson Frequency and time interval analyzer measurement hardware Hewlett-Packard J. pp. 35-411 Feb. 1989.
2. J. Kalisz and R. Szplet Time-to-digital converter with direct coding and 100 ps resolution Electron. Lett. vol. 31 pp. 1658-1659 1995.
3. Y. Aral and T. Oshugi TMC-A CMOS time to digital converter VLSI IEEE Trans. Nucl. Sci. vol. 36 pp. 528-531 1989.
4. T. Rahkonen and J. Kostamovaara The use of stabilized CMOS delay lines in the digitization of short time intervals in Proc. IEEE Symp. Circuits Syst. Singapore 1991 vol. 4 pp. 2252-2255; IEEE J. Solid-State Circuits vol. 28 pp. 887-894 1993.
5. G. D. Sasaki et ai 1.2 GHz GaAs shift register 1C for dead-time-less TDC application IEEE Trans. Nucl. Sci. vol. 36 pp. 512-516 1989.
6. J. Rose A. El Gamal and A. Sangiovanni-Vincentelli Architecture of field-programmable gate arrays Proc. IEEE vol. 81 pp. 1013-1029 1993.
7. S. D. Brown et al Field-Programmable Gate Arrays. Norwell MA: Kluwer 1992.
8. A. Rothermel and F. Dell'ova Analog phase measuring circuit for digital CMOS-ICs in Proc. ESSCIRC'92 Copenhagen Denmark 1992 pp. 331-334.
9. G. D. Sasaki and R. C. Jensen Automatic measurements with a high-performance universal counter Hewlett-Packard J. pp. 21-31 June 1980.
10. J. Kalisz M. Pawlowski and R. Pelka Error analysis and design of the Nutt time-interval digitiser with picosecond resolution J. Phys. E: Sci. Instrum. vol. 20 pp. 1330-1341 1987.
11. Very High Speed FPGAs. Santa Clara CA: QuickLogic 1995.
12. J. Kalisz R. Szplet R. Pelka and A. Poniecki Single-chip interpolating time counter with 200-ps resolution and 43-s range in Proc. IEEE Instrum. Meas. Technol. Conf. '96 Brussels 1996 pp. 676-680.