Bus-based integrated floorplanning

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages 875-878

  Rafiq, Faran ^a   Chrzanowska Jeske, Malgorzata ^b   Yang, Hannah Honghua ^a   Sherwani, Naveed ^a  

^a INTEL CORPORATION   (United States)

^b Portland State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; FUNCTIONS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; SIMULATED ANNEALING; VLSI CIRCUITS;

BUS BASED INTEGRATED FLOORPLANNING; BUS PLANNING; MIXED INTEGER LINEAR PROGRAMMING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036287385     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1011493     Document Type: Article

References (11)

1. Integrated floorplanning and interconnect planning
2. On convex formulation of the floorplan area minimization problem
3. Globally optimal floorplanning for a layout problem
4. Rectangle-packing based module placement
5. The channeled BSG: A universal floorplanner for simultaneous place/route with IC applications
6. Efficient floorplan optimization
7. Area minimization of general floorplans
8. Area minimization for general floorplans
9. A new algorithm for floorplan design
10. Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs