Placement with alignment and performance constraints using the B*-tree representation

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 568-571

  Wu, Meng Chen ^a   Chang, Yao Wen ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

AMORTIZED LINEAR-TIME COMPLEXITY; BENCHMARK CIRCUITS; DESIGN COMPLEXITY; PERFORMANCE CONSTRAINTS;

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DATA TRANSFER; MATHEMATICAL MODELS; SIMULATED ANNEALING; TREES (MATHEMATICS); VLSI CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 17644385254     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2004.1347979     Document Type: Conference Paper

References (15)

1. Y.C. Chang, Y.W. Chang, G.M. Wu, and S.W. Wu, "B*-trees: A new representation for non-slicing floorplans," Proc. DAC, pp. 458-463, 2000.
2. P.N. Guo, C.K. Cheng, and T. Yoshimura, "An O-tree representation of non-slicing floorplans and its applications," Proc. DAC, pp. 268-273, 1999.
3. J.M. Lin and Y.W. Chang, "TCG: A transitive closure graph-based representation for non-slicing floorplans," Proc. DAC, pp. 764-769, 2001.
4. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "Rectangle-packing based module placement," Proc. ICCAD, pp. 472-479, 1995.
5. S. Nakatake, H.Murata, K. Fujiyoshi, and Y. Kajitani, "VLSI module placement on BSG-structure and IC layour applications," Proc. ICCAD, pp. 484-491, 1996.
6. R.H.J.M. Otten, "Automatic floorplan design," Proc. DAC, pp. 261-267, 1982.
7. Y. Pang, C.-K. Cheng, K. Lampaert, and W. Xie, "Rectilinear block packing using O-tree representation," Proc. ISPD, pp. 156-161, 2001.
8. K. Sakanushi and Y. Kajitani, "The quarter-state sequence (Q-sequence) to represent the floorplan and applications to layout optimization," Proc. APCAS, pp. 829-832, 2000.
9. X. Tang, R. Tian, and D.F. Wong, "Fast evalution of sequence pair in block placement by longest common subsequence computation," Proc. DATE, pp. 106-111, 2000.
10. X. Tang and D.F. Wong, "FAST-SP: A fast algorithm for block placement based sequence pair," Proc. APS-DAC, pp. 521-526, 2001.
11. X. Tang and D.F. Wong, "Floorplanning with alignment and performance constraints," Proc. DAC, pp. 848-853, 2002.
12. D.F. Wong and C.L. Liu, "A new Algorithm for floorplan design," Proc. DAC, pp. 101-107, 1986.
13. J. Xu, P.-N. Guo, and C.-K. Cheng, "Rectilinear block placement using sequence-pair," Proc. ISPD. pp. 173-178, 1998.
14. B. Yao, H. Chen, C.-K. Cheng, and R. Graham, "Revisiting floorplan representations," Proc. ISPD, pp. 138-143, 2001.
15. F.Y. Young and D.F. Wong, "Slicing floorplans with range constraint," Proc. ISPD, pp. 97-102, 1999.