A 14-bit 20-MS/s pipelined ADC with digital distortion calibration

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Volumn , Issue , 2005, Pages 61-64

  Daito, Mutsuo ^a   Matsui, Hirofumi ^a   Ueda, Masaya ^a   Iizuka, Kunihiko ^a  

^a SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY CODES; CALIBRATION; CMOS INTEGRATED CIRCUITS; CONTROL NONLINEARITIES; DIGITAL CIRCUITS;

CALIBRATION PARAMETERS; DIGITAL DISTORTION; DIGITAL GAIN; SFDR; SNDR;

ANALOG TO DIGITAL CONVERSION;

EID: 34250697876     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2005.251807     Document Type: Conference Paper

References (7)

1. H.Chen, B.Son and K.Bacrania, "A14-b 20MSamples/s CMOS Pipelined ADC," IEEE J.Solid-State Circuits, vol.36, pp.997-1001, Jun. 2001.
2. Y.Chiu, P.R.Oray and B.Nikolic, "A 14-b 12-MS/s CMOS Pipeline ADC With Over 100-dB SFDR," IEEE J.Solid-State Circuits, vol.39, pp.2139-2151, Dec. 2004.
3. A.N.Karanicolas, H.S.Lee and K.L.Bacrania, "A15-b 1-MSample/s digitally self-calibrated pipeline ADC," IEEE J.Solid-State Circuits, vol.28, pp.1207-1215, Dec. 1993.
4. J.Ming and S.H.Lewis, "An 8-bit 80-Msample/s Pipelined Analog-to-Digtal Converter With Background Calibration," IEEE J.Solid-State Circuits, vol.36, pp.1489-1497, Dec. 2001.
5. B.Murman and B.E.Boser, "A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification," IEEE J.Solid-State Circuits, vol.38, pp.2040-2050, Dec. 2003.
6. C.R.Grace, P.J.Hurst and S.H.Lewis, "A 12b 80MS/S Pipelined ADC with Bootstrapped Digital Calibration," in ISSCC Dig. Tech. Papers, Feb. 2004.
7. H.Matsui, M.Ueda, M.Daito and K.Iizuka, "A 14bit Digitally Self-Calibrated Pipelined ADC with Adaptive Bias Optimization for Arbitrary Speeds up to 40MS/S," in Symp. VLSI Circuit Dig. Tech. Papers, Jun. 2005.