A 50MS/S (35mW) to 1kS/s (15μW) power scaleable 10b pipelined ADC with minimal bias current variation

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Ahmed, Imran ^a   Johns, David ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144461483     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. K. Gulati, H.S. Lee, "A Low-Power Reconfigurable Analog-to-Digital Converter,"IEEE J. Solid-State Circuits, vol 36, pp. 1900-1911, Dec., 2001.
2. B. Hernes et al., "A 1.2V 220MS/s 10b Pipeline ADC Implemented in 0.13μm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 256-257, Feb., 2004.
3. C. C.Enz and E. A.Vittoz, "CMOS Low-Power Analog Circuit Design," Proc. 1996 IEEE Int. Symp. Circuits and Systems (ISCAS'96), ch. 1.2, Tutorials, pp. 79-133.