On generating tests that avoid the detection of redundant faults in synchronous sequential circuits with full scan

IEEE Transactions on Computers

Volumn 55, Issue 4, 2006, Pages 491-495

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^b  

^a PURDUE UNIVERSITY   (United States)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

Design for testability; Fault dominance; Full scan; Overtesting; Redundant faults; Synchronous sequential circuits; Test generation

Indexed keywords

ERROR CORRECTION; ERROR DETECTION; FAILURE ANALYSIS; SEQUENTIAL CIRCUITS;

FAULT DOMINANCE; OVERTESTING; REDUNDANT FAULTS; SYNCHRONOUS SEQUENTIAL CIRCUITS; TEST GENERATION;

DESIGN FOR TESTABILITY;

EID: 33645242500     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2006.57     Document Type: Article

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