Low-cost sequential ATPG with clock-control DFT

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 243-248

  Abramovici, Miron ^a   Yu, Xiaoming ^b   Rudnick, Elizabeth M ^b  

^a AGERE SYSTEMS   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST-PATTERN GENERATION (ATPG);

ALGORITHMS; AUTOMATIC TESTING; COSTS; DELAY CIRCUITS; DESIGN FOR TESTABILITY; ELECTRIC CLOCKS; ELECTRIC FAULT CURRENTS; ENERGY DISSIPATION; FEEDBACK CONTROL;

SEQUENTIAL CIRCUITS;

EID: 0036058532     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012629     Document Type: Article

References (26)

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