Non-scan design for testability for synchronous sequential circuits based on conflict analysis

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 520-529

  Xiang, Dong ^a   Xu, Yi ^a   Fujiwara, Hideo ^b  

^a TSINGHUA UNIVERSITY   (China)

^b NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

CONFLICT ANALYSIS; FAULT EFFECT ACTIVATION; FAULT EFFECT PROPAGATION; SEQUENTIAL DEPTH FOR TESTABILITY; SYNCHRONOUS SEQUENTIAL CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 0034480245     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (24)