A new class of sequential circuits with combinational test generation complexity

IEEE Transactions on Computers

Volumn 49, Issue 9, 2000, Pages 895-905

  Fujiwara, Hideo ^a,b  

^a IEEE   (Japan)

^b NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Balanced structure; Complexity; Design for testability; Partial scan; Reducibility; Sequential circuits; Test generation

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; DESIGN FOR TESTABILITY; FINITE AUTOMATA; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; SEQUENTIAL MACHINES;

ACYCLIC STRUCTURE; BALANCED STRUCTURE; COMBINATIONAL TEST GENERATION COMPLEXITY; COMBINATIONAL TRANSFORMATION;

SEQUENTIAL CIRCUITS;

EID: 0034275158     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.869321     Document Type: Article

References (14)

1. H. Fujiwara, Logic Testing and Design for Testability. The MIT Press, 1985.
2. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, 1990.
3. R. Gupta, R. Gupta, and M.A. Breuer, "The BALLAST Methodology for Structured Partial Scan Design," IEEE Trans. Computers, vol. 39, no. 4, pp. 538-544, Apr. 1990.
4. A. Balakrishman and S.T. Chakradhar, "Sequential Circuits with Combinational Test Generation Complexity," Proc. IEEE Int'l Conf. VLSI Design, pp. 111-117, Jan. 1996.
5. A.D. Friedman and P.R. Menon, Theory and Design of Switching Circuits. Computer Science Press, 1975.
6. C.E. Leiserson and J.B. Saxe, "Retiming Synchronous Circuitry," Algorithmica, vol. 6, pp. 5-35, 1991.
7. K. Cheng and V.D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Trans. Computers, vol. 39, no. 4, pp. 544-548, Apr. 1990.
8. R. Gupta and M.A. Breuer, "Testability Properties of Acyclic Structures and Applications to Partial Scan Design," Proc. IEEE VLSI Test Symp., pp. 49-54, 1992.
9. D. Klagaris and S. Tragoudas, "Partial Scan with Retiming," Proc. Design Automation Conf., pp. 249-254, 1993.
10. S. Dey and S.T. Chakradhar, "Design of Testable Sequential Circuits by Repositioning Flip-Flops," J. Electronic Testing: Theory and Applications, vol. 7, pp. 105-114, 1995.
11. T. Takasaki, T. Inoue, and H. Fujiwara, "Partial Scan Design Methods Based on Internally Balanced Structure," Proc. Asia and South Pacific Design Automation Conf., pp. 211-216, Feb. 1998.
12. A. Balakrishnan and S.T. Chakradhar, "Software Transformations for Sequential Test Generation," Proc. IEEE Asian Test Symp., pp. 266-272, Nov. 1995.
13. A. El-Maleh, T.E. Marchok, J. Rajski, and W. Maly, "Behavior and Testability Preservation under the Retiming Transform," IEEE Trans. Computer-Aided Design, vol. 16, no. 5, pp. 528-543, May 1997.
14. S. Ohtake, T. Inoue, and H. Fujiwara, "Sequential Test Generation Based on Circuit Pseudo-Transformation," Proc. 1997 IEEE Asian Test Symp., pp. 62-67, Nov. 1997.