On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 867-872

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^b  

^a PURDUE UNIVERSITY   (United States)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DESIGN FOR TESTABILITY; ELECTRIC FAULT CURRENTS; MASKS; SET THEORY;

CIRCUIT OUTPUT; REDUNDANT FAULTS;

SEQUENTIAL CIRCUITS;

EID: 0346778704     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159777     Document Type: Conference Paper

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