Characteristics of body-tied triple-gate pMOSFETs

IEEE Electron Device Letters

Volumn 25, Issue 12, 2004, Pages 798-800

  Park, Tai Su ^a   Cho, Hye Jin ^b   Choe, Jeong Dong ^b   Cho, Il Hwan ^a   Park, Donggun ^b   Yoon, Euijoon ^a   Lee, Jong Ho ^c  

^a Seoul National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

^c Kyungpook National University   (South Korea)

Author keywords

Body tied; Bulk; FinFET; Omega; Triple gate

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRODES; LEAKAGE CURRENTS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS; THRESHOLD VOLTAGE;

BODY TIED MOSFET; FINFET; GATE ELECTRODES; TRIPLE GATE MOSFET;

MOSFET DEVICES;

EID: 10644280073     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.838060     Document Type: Article

References (9)

1. J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, and W. Haensch, "Metal-gate FinFET and fully depleted SOI divices using total gate silicidation," in IEDM Tech. Dig., Dec. 2002, pp. 247-250.
2. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J King, J. Boker, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling m 10 nm gate length," in IEDM Tech. Dig., Dec. 2002, pp. 251-254.
3. F.-L. Yang, H.-Y. Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang, H.-K. Chiu, C.-C. Lee, C.-C. Chen, H.-T. Huang, C.-J. Chen, H.-J. Tao, Y.-C. Yeo, M.-S. Liang, and C. Hu, "25 nm CMOS omega FETs," in IEDM Tech. Dig., Dec. 2002, pp. 255-258.
4. T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S. H. Hong, S. J. Hyun, Y. G. Shin, J. N. Han, I. S. Park, U. I. Chung, J. T. Moon, E. Yoon, and J. H. Lee, "Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers," in Symp. VLSI Tech. Dig., Kyoto, Japan, June 2003, pp. 135-136.
5. R. Katsumata, N. Tsuda, J. Idebuchi, M. Kondo, N. Aoki, S. Ito, K. Yahashi, T. Satonaka, M. Morikado, M. Kim, M. Kido, T. Tanaka, H. Aochi, and T. Hamannoto, "Fin-Array-FET on bulk silicon for sub-100 nm fin trench capacitor DRAM," in Symp. VLSI Tech. Dig., Kyoto, Japan, June 2003, pp. 61-62.
6. C. H. Lee, J. M. Yoon, C. Lee, H. M. Yang, K. N. Kim, T. Y. Kim, H. S. Kang, Y. J. Ahn, D. Park, and K. Kim, "Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60 nm technology and beyond," in Symp. VLSI Tech. Dig., Honolulu, HI, June 2004, pp. 130-131.
7. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub-50 nm FinFETs: PMOS," in IEDM Tech. Dig. Dec. 2002, pp. 67-70.
8. T. Park, D. Park, J. H. Chung, E. J. Yoon, S. M. Kim, H. J. Cho, J. D. Choe, J. H. Choi, B. M. Yoon, J. J. Han, B. H. Kim, S. Choi, K. Kim, E. Yoon, and J. H. Lee, "PMOS body-tied FinFET (Omega MOSFET) characteristics," in Proc. DRC, Salt Lake City, UT, June 2003, pp. 33-34.
9. J. Kedzierski, D. Boyd, Y. Zhang, M. Steen, F. F. Jamin, J. Benedict, M. Leong, and W. Haensuch, "Issues in NiSi-gated FDSOI device integration," in IEDM Tech. Dig., Dec. 2003, pp. 441-444.