-
1
-
-
0024750096
-
"A 20-MIPS sustained 32-bit CMOS microprocessor with high ratio of sustained to peak performance"
-
Oct.
-
N. P. Jouppi and J. Y.-F. Tang, "A 20-MIPS sustained 32-bit CMOS microprocessor with high ratio of sustained to peak performance," IEEE J.Solid State Circuits, vol. 24, no. 10, pp. 1348-1359, Oct. 1989.
-
(1989)
IEEE J.Solid State Circuits
, vol.24
, Issue.10
, pp. 1348-1359
-
-
Jouppi, N.P.1
Tang, J.Y.-F.2
-
2
-
-
0033697723
-
"On-chip decoupling capacitor optimization using architectural level current signature prediction"
-
Arlington, VA, Sep.
-
M. D. Pant, P. Pant, and D. S. Wills, "On-chip decoupling capacitor optimization using architectural level current signature prediction," in Proc. ASIC/SOC Conf., Arlington, VA, Sep. 2000, pp. 288-292.
-
(2000)
Proc. ASIC/SOC Conf.
, pp. 288-292
-
-
Pant, M.D.1
Pant, P.2
Wills, D.S.3
-
3
-
-
0031269882
-
"A 400-MHz S/390 microprocessor"
-
Nov.
-
C. F. Webb et al., "A 400-MHz S/390 microprocessor," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1665-1672, Nov. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.11
, pp. 1665-1672
-
-
Webb, C.F.1
-
4
-
-
0036589484
-
"Frequency dependences of power noise"
-
May
-
B. Garben, R. Frech, J. Supper, and M. F. McAllister, "Frequency dependences of power noise," IEEE Trans. Adv. Packag., vol. 25, no. 2, pp. 166-173, May 2002.
-
(2002)
IEEE Trans. Adv. Packag.
, vol.25
, Issue.2
, pp. 166-173
-
-
Garben, B.1
Frech, R.2
Supper, J.3
McAllister, M.F.4
-
5
-
-
0034317260
-
"The first IA-64 microprocessor"
-
Nov.
-
S. Rusu and G. Singer, "The first IA-64 microprocessor," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1539-1544, Nov. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.11
, pp. 1539-1544
-
-
Rusu, S.1
Singer, G.2
-
6
-
-
0034315885
-
"A third-generation SPARC V9 64-b microprocessor"
-
Nov.
-
R. Heald et al., "A third-generation SPARC V9 64-b microprocessor," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1526-1538, Nov. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.11
, pp. 1526-1538
-
-
Heald, R.1
-
7
-
-
0032071753
-
"High-performance microprocessor design"
-
May
-
P. E. Gronowski, W. J. Bowhill, R. P. Preston, M. K. Gowan, and R. L. Allmon, "High-performance microprocessor design," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 676-686, May 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, Issue.5
, pp. 676-686
-
-
Gronowski, P.E.1
Bowhill, W.J.2
Preston, R.P.3
Gowan, M.K.4
Allmon, R.L.5
-
8
-
-
0344089095
-
"Optimal decoupling capacitor sizing and placement for standard-cell layout designs"
-
Apr.
-
H. Su, S. Sapatnekar, and S. R. Nassif, "Optimal decoupling capacitor sizing and placement for standard-cell layout designs," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 22, no. 4, pp. 428-436, Apr. 2003.
-
(2003)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
, vol.22
, Issue.4
, pp. 428-436
-
-
Su, H.1
Sapatnekar, S.2
Nassif, S.R.3
-
9
-
-
84945375645
-
"On-chip decoupling capacitor optimization for noise and leakage reduction"
-
Sep.
-
H. H. Chen, J. S. Neely, M. F. Wang, and G. Co, "On-chip decoupling capacitor optimization for noise and leakage reduction," in Proc. 16th Symp. Integrated Circuits and Systems Design, Sep. 2003, pp. 251-255.
-
(2003)
Proc. 16th Symp. Integrated Circuits and Systems Design
, pp. 251-255
-
-
Chen, H.H.1
Neely, J.S.2
Wang, M.F.3
Co, G.4
-
10
-
-
0036179950
-
"Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning"
-
Jan.
-
S. Zhao, K. Roy, and C.-K. Koh, "Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 1, pp. 81-92, Jan. 2002.
-
(2002)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
, vol.21
, Issue.1
, pp. 81-92
-
-
Zhao, S.1
Roy, K.2
Koh, C.-K.3
-
11
-
-
0031118098
-
"Parasitic resistance in a MOS transistor used as on-chip decoupling capacitance"
-
Apr.
-
P. Larsson, "Parasitic resistance in a MOS transistor used as on-chip decoupling capacitance," IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 574-576, Apr. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.4
, pp. 574-576
-
-
Larsson, P.1
-
12
-
-
15944419208
-
"A model for on-chip decoupling capacitor effectiveness including gate leakage effects"
-
Portland, OR
-
J. Rius and M. Meijer, "A model for on-chip decoupling capacitor effectiveness including gate leakage effects," in Dig. IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, Portland, OR, 2004, pp. 299-302.
-
(2004)
Dig. IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging
, pp. 299-302
-
-
Rius, J.1
Meijer, M.2
-
14
-
-
0010436440
-
"Large signal transit-time effects in the MOS transistor"
-
Mar.
-
J. R. Burns, "Large signal transit-time effects in the MOS transistor," RCA Rev., vol. 29, pp. 15-35, Mar. 1969.
-
(1969)
RCA Rev.
, vol.29
, pp. 15-35
-
-
Burns, J.R.1
-
15
-
-
0035250093
-
"Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current"
-
Feb.
-
M. Koh and W. Mizubayashi et al., "Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current," IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 259-264, Feb. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, Issue.2
, pp. 259-264
-
-
Koh, M.1
Mizubayashi, W.2
-
16
-
-
0042697357
-
"Gate current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits"
-
Feb.
-
K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Gate current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
-
(2003)
Proc. IEEE
, vol.91
, Issue.2
, pp. 305-327
-
-
Roy, K.1
Mukhopadhyay, S.2
Mahmoodi-Meimand, H.3
-
18
-
-
0003552050
-
International Roadmap for Semiconductors
-
Semiconductor Industry Association. [Online] Available:
-
International Roadmap for Semiconductors. Semiconductor Industry Association. [Online] Available: http://public.itrs.net/
-
-
-
-
19
-
-
10044250104
-
"Modeling the dynamic response of on-chip decoupling capacitors"
-
Heidelberg, Germany
-
J. Rius and M. Meijer, "Modeling the dynamic response of on-chip decoupling capacitors," in Proc. 8th Workshop on Signal Propagation on Interconnects, Heidelberg, Germany, 2004, pp. 39-42.
-
(2004)
Proc. 8th Workshop on Signal Propagation on Interconnects
, pp. 39-42
-
-
Rius, J.1
Meijer, M.2
-
20
-
-
0033342063
-
"A large signal nonquasi-static MOS model for RF circuit simulation"
-
Washington, DC
-
A. J. Scholten, L. F. Tiemeijer, P. W. H. de Vreede, and D. B. M. Klaassen, "A large signal nonquasi-static MOS model for RF circuit simulation," in IEDM Tech. Dig., Washington, DC, 1999, pp. 163-166.
-
(1999)
IEDM Tech. Dig.
, pp. 163-166
-
-
Scholten, A.J.1
Tiemeijer, L.F.2
de Vreede, P.W.H.3
Klaassen, D.B.M.4
-
21
-
-
6344220868
-
MOS model 11
-
[Online] Available:
-
MOS model 11. [Online] Available: http://www.semiconductors.philips.com/ Philips_Models/mos_models/model11
-
-
-
|