First IA-64 microprocessor

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 11, 2000, Pages 1539-1544

  Rusu, Stefan ^a,b   Singer, Gadi ^a  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY POLITEHNICA OF BUCHAREST   (Romania)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DESIGN FOR TESTABILITY; ELECTRONICS PACKAGING; FLIP CHIP DEVICES; INTEGRATED CIRCUIT MANUFACTURE; PARALLEL PROCESSING SYSTEMS;

EXPLICITLY PARALLEL INSTRUCTION COMPUTING; MACHINE CHECK ARCHITECTURE; SOURCE SYNCHRONOUS BUS;

MICROPROCESSOR CHIPS;

EID: 0034317260     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.881197     Document Type: Article

References (6)

1. G. Singer and S. Rusu, "The first IA-64 microprocessor - A design for highly parallel execution," ISSCC Dig. Tech. Papers, pp. 422-423, Feb. 2000.
2. T. Ghani et al., "100 nm gate-length high-performance low-power CMOS transistor structure," IEDM Tech. Dig., pp. 415-418, Dec. 1999.
3. D. Harris et al., "Skew-tolerant domino circuits," in IEEE J. Solid State Circuits, vol. 32, Nov. 1997, pp. 1702-1711.
4. [4) S. Rusu and S. Tam, "Clock generation and distribution for the first IA-64 microprocessor," ISSCC Dig. Tech. Papers, pp. 176-177, Feb. 2000.
5. I. Young et al., "A 0.35 μm CMOS 3-880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors," in ISSCC Dig. Tech. Papers, 1997, pp. 330-331.
6. R. Senthinathan et al., "A 650-MHz, IA-32 microprocessor with enhanced data streaming for graphics and video," IEEE J. Solid-State Circuits, vol. 34, pp. 1454-1465, Nov. 1999.