On-chip decoupling capacitor optimization using architectural level current signature prediction

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2000, Pages 288-297

  Pant, Mondira Deb ^a   Pant, Pankaj ^a   Wills, Donald Scott ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; COMPUTER SIMULATION; ENERGY STORAGE; MATHEMATICAL MODELS; OPTIMIZATION; PROGRAM PROCESSORS; SPURIOUS SIGNAL NOISE; SWITCHING CIRCUITS;

DECOUPLING CAPACITORS; MICROARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 0033697723     PISSN: 10630988     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASIC.2000.880751     Document Type: Article

References (0)