Physical modelling strategy for (quasi-) saturation effects in lateral DMOS transistor based on the concept of intrinsic drain voltage

Proceedings of the International Semiconductor Conference, CAS

Volumn 2, Issue , 2001, Pages 417-420

  Anghel, C ^a   Hefyene, N ^a   Ionescu, A M ^a   Vermandel, M ^a   Bakeroot, B ^a   Doutreloigne, J ^a   Gillon, R ^a   Frere, S ^a   Maier, C ^a   Mourier, Y ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; SEMICONDUCTOR DEVICE MODELS;

DRAIN CURRENT; INTRINSIC DRAIN VOLTAGE; SATURATION EFFECT;

MOSFET DEVICES;

EID: 0035744379     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. New physical insights and models for high-voltage LDMOS IC CAD
2. Circuit model for power LDMOS including quasi-saturation