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Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 43, Issue 4 B, 2004, Pages 2145-2150

A high-aspect-ratio silicon gate formation technique for beam-channel MOS transistor with impurity-enhanced oxidation

(3) Katakami, Akira a,b Kobayashi, Kei a Sunami, Hideo a

a HIROSHIMA UNIVERSITY (Japan)

b FUJITSU LABORATORIES LTD (Japan)

Author keywords

Beam channel transistor; Impurity enhanced oxidation; Silicon gate; Three dimensional structure

Indexed keywords

ANISOTROPY; CMOS INTEGRATED CIRCUITS; DIELECTRIC FILMS; DRY ETCHING; ELECTRODES; ELECTRON CYCLOTRON RESONANCE; MOSFET DEVICES; OXIDATION; POLYSILICON; REACTIVE ION ETCHING; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DOPING;

BEAM-CHANNEL TRANSISTORS (BCT); IMPURITY-ENHANCED OXIDATION; LIGHTLY-DOPED DRAIN (LDD); SILICON GATES; THREE-DIMENSIONAL STRUCTURES;

MOS DEVICES;

EID: 3142571040 PISSN: 00214922 EISSN: None Source Type: Journal
DOI: 10.1143/JJAP.43.2145 Document Type: Conference Paper

Times cited : (5)

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