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Volumn , Issue , 2004, Pages 335-339

Low power repeaters driving RC interconnects with delay and bandwidth constraints

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH CONSTRAINTS; BERKELEY PREDICTIVE TECHNOLOGY MODEL (BPT); POWER DISSIPATION; SHORT-CIRCUIT POWER;

EID: 14844334570     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (12)

References (14)
  • 1
    • 0022061669 scopus 로고
    • Optimal interconnection circuits for VLSI
    • May
    • H. B. Bakoglu and J. D. Meindl, "Optimal Interconnection Circuits for VLSI," IEEE Transactions on Electron Devices, Vol. ED-32, No. 5, pp. 903-909, May 1985.
    • (1985) IEEE Transactions on Electron Devices , vol.ED-32 , Issue.5 , pp. 903-909
    • Bakoglu, H.B.1    Meindl, J.D.2
  • 2
    • 0036046921 scopus 로고    scopus 로고
    • Power estimation in global interconnects and its reduction using a novel repeater optimization methodology
    • June
    • P. Kapur, G. Chandra, and K. C. Saraswat, "Power Estimation in Global Interconnects and Its Reduction Using a Novel Repeater Optimization Methodology," Proceedings of the ACM/IEEE Design Automation Conference, pp. 461-466, June 2002.
    • (2002) Proceedings of the ACM/IEEE Design Automation Conference , pp. 461-466
    • Kapur, P.1    Chandra, G.2    Saraswat, K.C.3
  • 4
    • 0034771119 scopus 로고    scopus 로고
    • A practical approach to DSM repeater insertion: Satisfying delay constraints while minimizing area and power
    • September
    • A. Nalamalpu and W. Burleson, "A Practical Approach to DSM Repeater Insertion: Satisfying Delay Constraints while Minimizing Area and Power," Proceedings of the IEEE ASIC/SOC Conference, pp. 152-156, September 2001.
    • (2001) Proceedings of the IEEE ASIC/SOC Conference , pp. 152-156
    • Nalamalpu, A.1    Burleson, W.2
  • 5
    • 0036866915 scopus 로고    scopus 로고
    • A power-optimal repeater insertion methodology for global interconnects in nanometer designs
    • November
    • K. Banerjee and A. Mehrotra, "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs," IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 2001-2007, November 2002.
    • (2002) IEEE Transactions on Electron Devices , vol.49 , Issue.11 , pp. 2001-2007
    • Banerjee, K.1    Mehrotra, A.2
  • 9
    • 0027222295 scopus 로고
    • Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's
    • Januanry
    • T. Sakurai, "Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's," IEEE Transactions on Electron Devices, Vol. 40, No. 1, pp. 118-124, Januanry 1993.
    • (1993) IEEE Transactions on Electron Devices , vol.40 , Issue.1 , pp. 118-124
    • Sakurai, T.1
  • 10
    • 0025415048 scopus 로고
    • Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
    • April
    • T. Sakurai and A. R. Newtion, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, pp. 584-594, April 1990.
    • (1990) IEEE Journal of Solid-state Circuits , vol.25 , Issue.2 , pp. 584-594
    • Sakurai, T.1    Newtion, A.R.2
  • 11
    • 0032142155 scopus 로고    scopus 로고
    • On-chip crosstalk noise model for deep-submicrometer ULSI interconnect
    • August
    • S. O. Nakagawa et al., "On-Chip Crosstalk Noise Model for Deep-Submicrometer ULSI Interconnect," The Hewlett-Packard Journal, pp. 39-45, August 1998.
    • (1998) The Hewlett-Packard Journal , pp. 39-45
    • Nakagawa, S.O.1
  • 13
    • 0033891230 scopus 로고    scopus 로고
    • Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
    • April
    • Y. I. Ismail and E. G. Friedman, "Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 2, pp. 195-206, April 2000.
    • (2000) IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.8 , Issue.2 , pp. 195-206
    • Ismail, Y.I.1    Friedman, E.G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.