Sensitivity of interconnect delay to on-chip inductance

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2000, Pages

  Ismail, Yehea I ^a   Friedman, Eby G ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ERROR ANALYSIS; INDUCTANCE MEASUREMENT; MATHEMATICAL MODELS; WAVEFORM ANALYSIS;

ON-CHIP INDUCTANCE;

INTERCONNECTION NETWORKS;

EID: 0033699498     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.856082     Document Type: Conference Paper

References (22)