Algorithmic aspects of hardware/software partitioning

ACM Transactions on Design Automation of Electronic Systems

Volumn 10, Issue 1, 2005, Pages 136-156

  Arató, Péter ^a   Mann, Zoltán Ádám ^a   Orbán, András ^a  

^a BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS   (Hungary)

Author keywords

Graph algorithms; Graph bipartitioning; Hardware software codesign; Hardware software partitioning; Optimization

Indexed keywords

EID: 30544446741     PISSN: 10844309     EISSN: 10844309     Source Type: Journal    
DOI: 10.1145/1044111.1044119     Document Type: Article

References (44)

1. ABDELZAHER, T. F. AND SHIN, K. G. 2000. Period-based load partitioning and assignment for large real-time applications. IEEE Trans. Comput. 49, 1, 81-87.
2. AHUJA, R. K., MAGNANTI, T. L., AND ORLIN, J. B. 1993. Network Flows: Theory, Algorithms, and Applications. Prentice-Hall, Englewood Cliffs, NJ.
3. ARATÓ, P., JUHÁSZ, S., MANN, Z. Á., ORBÁN, A., AND PAPP, D. 2003a. Hardware/software partitioning in embedded system design. In Proceedings of the IEEE International Symposium on Intelligent Signal Processing.
4. ARATÓ, P., MANN, Z. Á., AND ORBÁN, A. 2003b. Hardware-software co-design for Kohonen's self-organizing map. In Proceedings of the IEEE 7th International Conference on Intelligent Engineering Systems.
5. BARROS, E., ROSENSTIEL, W., AND XIONG, X. 1993. Hardware/software partitioning with UNITY. In Proceedings of the 2nd International Workshop on Hardware-Software Codesign.
6. BINH, N. N., IMAI, M., SHIOMI, A., AND HIKICHI, N. 1996. A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts. In Proceedings of the 33rd Design Automation Conference.
7. CHATHA, K. S. AND VEMURI, R. 2001. MAGELLAN: Multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. In Proceedings of CODES 01.
8. CHERKASSKY, B. V. AND GOLDBERG, A. V. 1997. On implementing push-relabel method for the maximum flow problem. Algorithmica 19, 4, 390-410.
9. DASDAN, A. AND AYKANAT, C. 1997. Two novel multiway circuit partitioning algorithms using relaxed locking. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 16, 2 (Feb.), 169-177.
10. DICK, R. P. AND JHA, N. K 1998. MOGAC: A multiobjective genetic algorithm for hardware-software co-synthesis of hierarchical heterogeneous distributed embedded systems. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 17, 10, 920-935.
11. ELES, P., PENG, Z., KUCHCINSKI, K, AND DOBOLI, A. 1996. Hardware/ software partitioning of VHDL system specifications. In Proceedings of EURO-DAC '96.
12. ELES, P., PENG, Z., KUCHCINSKI, K., AND DOBOLI, A. 1997. System level hardware/software partitioning based on simulated annealing and tabu search. Des. Automat. Embedd. Syst. 2, 1 (Jan.), 5-32.
13. ERNST, R., HENKEL, J., AND BENNER, T. 1993. Hardware/software cosynthesis for microcontrollers. IEEE Des. Test Comp. 10, 4, 64-75.
14. FIDUCCIA, C. M. AND MATTHEYSES, R. M. 1982. A linear-time heuristic for improving network partitions. In Proceedings of the 19th Design Automation Conference.
15. GAREY, M. R. AND JOHNSON, D. S. 1979. A Guide to the Theory of NP-Completeness. Freeman, San Francisco, CA.
16. GOLDBERG, A. V. AND TARJAN, R. E. 1988. A new approach to the maximum flow problem. J. Assoc. Comput. Mach. 35, 921-940.
17. GRODE, J., KNUDSEN, P. V., AND MADSEN, J. 1998. Hardware resource allocation for hardware/software partitioning in the LYCOS system. In Proceedings of Design Automation and Test in Europe (DATE '98).
18. GUPTA, R. K. AND DE MICHELI, G. 1993. Hardware-software cosynthesis for digital systems. IEEE Des. Test Comp. 10, 3, 29-41.
19. GUTHAUS, M. R., RINGENBERG, J. S., ERNST; D., AUSTIN, T. M., MUDGE, T., AND BROWN, R. B. 1997. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the IEEE 4th Annual Workshop on Workload Characterization.
20. HENKEL, J. AND ERNST, R. 2001. An approach to automated hardware/ software partitioning using a flexible granularity that is driven by high-level estimation techniques. IEEE Trans. VLSI Syst. 9, 2, 273-289.
21. KALAVADE, A. 1995. System-level codesign of mixed hardware-software systems. Ph.D. dissertation. University of California, Berkeley, Berkeley, CA.
22. KALAVADE, A. AND LEE, E. A. 1997. The extended partitioning problem: Hardware/Software mapping, scheduling and implementation-bin selection. Des. Automat. Embedd. Syst. 2, 2, 125-164.
23. KALAVADE, A. AND SUBRAHMANYAM, P. A. 1998. Hardware/software partitioning for multifunction systems. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 17, 9 (Sept.), 819-837.
24. KERNIGHAN, B. W. AND LIN, S. 1970. An efficient heuristic procedure for partitioning graphs. Bell Syst. Techn. J. 49, 2, 291-307.
25. LOPEZ-VALLEJO, M., GRAJAL, J., AND LOPEZ, J. C. 2000. Constraint-driven system partitioning. In Proceedings of DATE. 411-416.
26. LOPEZ-VALLEJO, M. AND LOPEZ, J. C. 1998. A knowledge based system for hardware-software partitioning. In Proceedings of DATE.
27. LOPEZ-VALLEJO, M. AND LOPEZ, J. C. 2003. On the hardware-software partitioning problem: System modeling and partitioning techniques. ACM Trans. Des. Automat. Electron. Syst. 8, 3 (July), 269-297.
28. MADSEN, J., GRODE, J., KNUDSEN, P. V., PETERSEN, M. E., AND HAXTHAUSEN, A. 1997. LYCOS: The Lyngby co-synthesis system. Des. Automat. Embedd. Syst. 2, 2, 195-236.
29. MANN, Z. Á. AND ORBÁN, A. 2003. Optimization problems in system-level synthesis. In Proceedings of the 3rd Hungarian-Japanese Symposium on Discrete Mathematics and Its Applications.
30. MEI, B., SCHAUMONT, P., AND VERNALDE, S. 2000. A hardware/software partitioning and scheduling algorithm for dynamically reconfigurable embedded systems. In Proceedings of ProRISC.
31. NIEMANN, R. 1998. Hardware/Software Co-Design for Data Flow Dominated Embedded Systems. Kluwer Academic Publishers, Norwell, MA.
32. NIEMANN, R. AND MARWEDEL, P. 1997. An algorithm for hardware/software partitioning using mixed integer linear programming. Des. Automat. Embedd. Syst. Special Issue: Partitioning Methods for Embedded Systems 2, 165-193.
33. O'NILS, M., JANTSCH, A., HEMANI, A., AND TENHUNEN, H. 1995. Interactive hardware-software partitioning and memory allocation based on data transfer profiling. In Proceedings of the International Conference on Recent Advances in Mechatronics.
34. QIN, S. AND HE, J. 2000. An algebraic approach to hardware/software partitioning. Tech. rep. 206, UNU/IIST.
35. QUAN, G., HU, X., AND GREENWOOD, G. 1999. Preference-driven hierarchical hardware/software partitioning. In Proceedings of the IEEE/ACM International Conference on Computer Design.
36. SAAB, Y. G. 1995. A fast and robust network bisection algorithm. IEEE Trans. Comput. 44, 7 (July), 903-913.
37. SRINIVASAN, V., RADHAKRISHNAN, S., AND VEMURI, R. 1998. Hardware software partitioning with integrated hardware design space exploration. In Proceedings of DATE.
38. STITT, G., LYSECKY, R., AND VAHID, F. 2003. Dynamic hardware/software partitioning: A first approach. In Proceedings of DAC.
39. STONE, H. 1977. Multiprocessor scheduling with the aid of network flow algorithms. IEEE Trans. Softw. Eng. 3, 1 (Jan.), 85-93.
40. VAHID, F. 1997. Modifying min-cut for hardware and software functional partitioning. In Proceedings of the International Workshop on Hardware-Software Codesign.
41. VAHID, F. 2002. Partitioning sequential programs for CAD using a three-step approach. ACM Trans. Des. Automat. Electron. Syst. 7, 3 (July), 413-429.
42. VAHID, F. AND GAJSKI, D. 1995. Clustering for improved system-level functional partitioning. In Proceedings of the 8th International Symposium on System Synthesis.
43. VAHID, F. AND LE, T. D. 1997. Extending the Kernighan/Lin heuristic for hardware and software functional partitioning. Des. Automat. Embedd. Syst. 2, 237-261.
44. WOLF, W. H. 1997. An architectural co-synthesis algorithm for distributed embedded computing systems. IEEE Trans. VLSI Syst. 5, 2 (June), 218-229.