Hardware/software partitioning for multifunction systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 9, 1998, Pages 819-837

  Kalavade, Asawaree ^a,b   Subrahmanyam, P A ^a,b  

^a LUCENT TECHNOLOGIES   (United States)

^b Stanford University ^*  (United States)

Author keywords

Hardware software codesign; Hardware software partitioning; Multifunction systems; System level design; Video encode decode

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER SOFTWARE; IMAGE CODING;

MULTIFUNCTION SYSTEMS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0032166182     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.720318     Document Type: Article

References (15)

1. A. Kalavade and E. A. Lee, "The extended partitioning problem: Hardware/software mapping, scheduling, and implementation-bin selection," J. Design Automat. Embedded Syst., vol. 2, no. 2, pp. 226-163, Mar. 1997. [OnlineJ. Available WWW: http://www.belllabs.com/user/kalavade/papers/pdf/daem-partitioning.pdf.
2. J. Buck, S. Ha, E. A. Lee, and D. G. Messerschmitt, "Ptolemy: A framework for simulating and prototyping heterogeneous systems," Int. J. Comput. Simulation, vol. 4, pp. 155-182, Apr. 1994.
3. A. Kalavade and E. A. Lee, "A hardware/software codesign methodology for DSP applications," IEEE Design Test Comput. Mag., pp. 16-28, Sept. 1993.
4. A. Kalavade, "System-level codesign of mixed hardware-software systems," Ph.D. dissertation, University of California, Berkeley, CA, Sept. 1995.
5. J. M. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of datapath-intensive architectures," IEEE Design Test Comput. Mag., pp. 40-51, June 1991.
6. J. Sato, A. Y. Alomary, Y. Honma, and T. Nakata, "PEAS-I: A hardware/software codesign system for ASIP development," IEICE Trans. Fundamentals Electron., Commun. Comput. Sci., vol. E77-A, no. 3, pp. 483-91, Mar. 1994.
7. N. Ngoc, M. Imai, A. Shiomi, and N. Hikichi, "A hardware/software partitioning algorithm for designing pipelined ASIP's with least gate counts," in Proc. 33rd DAC, June 1996, pp. 527-532.
8. J. Van Praet, G. Goossens, D. Lanneer, and D. H De Man, "Instruction set definition and instruction selection for ASIP's," in Proc. 7th Int. Symp. High-Level Synthesis, Niagara-on-the-Lake, Canada, 1994, pp. 11-16.
9. H. Ing-Jer and A. M. Despain, "Generating instruction sets and microarchitectures from applications," in Proc. ICCAD 94, pp. 391-396.
10. P. Paulin, C. Liem, T. May, and S. Sutarwala, "DSP design tool requirements for embedded systems: A telecommunications industrial perspective," J. VLSI Signal Process., vol. 9, no. 1/2, pp. 23-417, Jan. 1995.
11. W. Zhao and C. A. Papachristou, "Synthesis of reusable DSP core based on multiple behaviors," in Proc. ICCAD 96, pp. 103-109.
12. M. Potkonjak and W. Wolf, "Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques," in Proc. ICCAD 95, pp. 446-151.
13. A. Kalavade and P. Moghe, "A tool for performance estimation o networked embedded systems," in Proc. DAC, June 1998, pp. 257-262.
14. D. Rao and F. Kurdahi, "Partitioning by regularity extraction," in Proc 29th DAC, 1992, pp. 235-238.
15. L. Guerra, M. Potkonjak, and J. Rabaey, "System-level design guidance using algorithm properties," VLSI Signal Processing VII, J. Rabaey, P. M. Chau, and J. Eldon, Eds. New York: IEEE Press, 1994.