Effects of circuit-level stress on inverter performance and MOSFET characteristics

IEEE International Integrated Reliability Workshop Final Report

Volumn 2003-January, Issue , 2003, Pages 71-79

  Stutzke, N ^a   Cheek, B J ^a   Kumar, S ^b   Baker, R J ^a   Moll, A J ^c   Knowlton, W B ^a  

^a BOISE STATE UNIVERSITY   (United States)

^b CYPRESS SEMICONDUCTOR   (United States)

^c Boise State University   (United States)

Author keywords

Circuit simulation; Degradation; Inverters; Leakage current; MOSFET circuits; Stress; Switches; Switching circuits; Threshold voltage; Transconductance

Indexed keywords

CIRCUIT SIMULATION; COMPUTER CIRCUITS; DEGRADATION; DELAY CIRCUITS; ELECTRIC INVERTERS; GATES (TRANSISTOR); LEAKAGE CURRENTS; MOSFET DEVICES; TIMING CIRCUITS; TRANSCONDUCTANCE;

CIRCUIT LEVELS; FALL TIME; GATE OXIDE THICKNESS; INVERTER; INVERTER OPERATIONS; MOSFET CIRCUITS; MOSFETS; PERFORMANCE; RAMPED VOLTAGE STRESS; VOLTAGE TRANSFER CURVES;

THRESHOLD VOLTAGE;

EID: 3042612561     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: 10.1109/IRWS.2003.1283304     Document Type: Conference Paper

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