Full-chip multilevel routing for power and signal integrity

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 1116-1121

  Xiong, Jinjun ^a   He, Lei ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; CONSTRAINT THEORY; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER DISTRIBUTION; ELECTRIC WIRE; FEEDBACK; BENCHMARKING; EXHIBITIONS; ITERATIVE METHODS;

SIGNAL INTEGRITY; SIGNAL NETWORKS; SIGNAL ROUTING;

ELECTRIC POWER TRANSMISSION NETWORKS; DESIGN;

ALTERNATIVE DESIGNS; DEEP SUB-MICRON DESIGNS; DESIGN CONVERGENCE; DESIGN METHODOLOGY; ESTIMATION FORMULAE; INTEGRITY CONSTRAINTS; NOVEL DESIGN METHODOLOGY; POWER AND SIGNAL INTEGRITIES;

EID: 3042515367     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. C. Alpert. The ISPD98 circuit benchmark suite. In ISPD, 1998.
2. B. Chappell, X. Wang, P. Patra, P. Saxena, J. Vendrell, S. Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, and S. Jain. A system-level solution to domino synthesis with 2 GHz application. In Proc. IEEE Int. Conf. on Computer Design, pages 164-171, Sept. 2002.
3. J. Cong, J. Fang, and Y. Zhang. Multilevel approach to full-chip gridless routing. In ICCAD, pages 396-403, 2001.
4. R. Hadsell and P. Madden. Improved global routing through congestion estimation. In DAC, 2003.
5. J. Hu and S. S. Sapatnekar. A timing-constrained algorithm for simultaneous global routing of multiple nets. In Proc. Int. Conf. on Computer Aided Design, pages 99-103, 2000.
6. R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh. Predictable routing. In ICCAD, 2000.
7. R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh. An exact algorithm for coupling-free routing. In ISPD, 2001.
8. J. Lillis, C. K. Cheng, T. T. Y. Lin, and C. Y. Ho. New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing. In Proc. Design Automation Conf, pages 395-400, June 1996.
9. S.-P. Lin and Y.-W. Chang. A novel framework for multilevel routing considering routability and performance. In ICCAD, pages 44-50, 2002.
10. P. Saxena and S. Gupta. On integrating power and signal routing for shield count minimization in congested regions. TCAD, April 2003.
11. A. Sinha and S. Chowdhury. Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast r, 1 extraction. In Proc. IEEE Int. Conf. on Custom Integrated Circuits, pages 461-465, 1999.
12. H. Su, J. Hu, S. Sapatnekar, and S. Nassif. Congestion-driven codesin of power and signal networks. In Proc. Design Automation Conf, pages 64-69, 2002.
13. H.-P. Tseng, L. Scheffer, and C. Sechen. Timing- and crosstalk-driven area routing. April 2001.
14. K. Wang and M. Marek-Sadowska. On-chip power supply network optimization using multigrid-based technique. In Proc. Design Automation Conf, 2003.
15. M. Wang, X. Yang, and M. Sarrafzadeh. DRAGON2000: Standard-cell placement tool for large industry circuits. In ICCAD, 2000.
16. J. Xiong, J. Chen, J. Ma, and L. He. Post global routing optimization with RLC crosstalk constraints. In ICCAD, 2002.
17. T. Xue and E. S. Kuh. Post global routing crosstalk synthesis. TCAD, pages 1418-1430, Dec. 1997.
18. H. Zhou and D. F. Wong. Global routing with crosstalk constraints. TCAD, November 1999.