Efficient metrics and high-level synthesis for dynamically reconfigurable logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 6, 2004, Pages 603-621

  Meribout, Mahmoud ^a,b   Motomura, Masato ^a  

^a NEC CORPORATION   (Japan)

^b SULTAN QABOOS UNIVERSITY   (Oman)

Author keywords

Allocation; Communication cost; Dynamic reconfigurable logic; Multiplexer cost; Partitioning; Scheduling

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COSTS; LOGIC DESIGN; LOGIC GATES; MATHEMATICAL MODELS; MULTIMEDIA SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; SCHEDULING; STATIC RANDOM ACCESS STORAGE;

ALLOCATION; COMMUNICATION COSTS; DYNAMIC RECONFIGURABLE LOGIC; MULTIPLEXER COSTS; PARTIONING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 3042513349     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.827564     Document Type: Article

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