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Volumn 36, Issue 10, 1998, Pages 127-131

VLSI for OFDM

Author keywords

[No Author keywords available]

Indexed keywords


EID: 0002616354     PISSN: 01636804     EISSN: None     Source Type: Journal    
DOI: 10.1109/35.722148     Document Type: Article
Times cited : (58)

References (15)
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  • 2
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  • 3
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    • Edfors, O.1
  • 4
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    • FDF, a 512-TAP FIR Filter Using a Mixed Temporal-Frequential Approach
    • Santa Clara, CA, May
    • E. Bidet et al., "FDF, a 512-TAP FIR Filter Using a Mixed Temporal-Frequential Approach," Proc. 1995 IEEE Custom Integrated Circuits Conf., Santa Clara, CA, May, 1995, pp. 173-76.
    • (1995) Proc. 1995 IEEE Custom Integrated Circuits Conf. , pp. 173-176
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  • 5
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    • Design and Implementation of a 1024-point Pipeline FFT Processor
    • Santa Clara, CA, May
    • S, He and M. Torkelson, "Design and Implementation of a 1024-point Pipeline FFT Processor," Proc. 1998 IEEE Custom Integrated Circuits Conf., Santa Clara, CA, May, 1998, pp. 131-34.
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    • He, S.1    Torkelson, M.2
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    • May
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    • Wold, E.H.1    Despain, A.M.2
  • 7
    • 0031634125 scopus 로고    scopus 로고
    • A Single Chip DMT Modem for High-Speed WLANs
    • Santa Clara, CA, May
    • T Arivoli et al., "A Single Chip DMT Modem for High-Speed WLANs," Proc 1998 IEEE Custom Integrated Circuits Conf., Santa Clara, CA, May 1998, pp. 9-11, http://www.radiata.com
    • (1998) Proc 1998 IEEE Custom Integrated Circuits Conf. , pp. 9-11
    • Arivoli, T.1
  • 8
    • 0009554784 scopus 로고
    • A Comparison of Path Memory Techniques for VLSI Viterbi Decoders
    • Munich, Germany, Sept.
    • D. J. Coggins et al., "A Comparison of Path Memory Techniques for VLSI Viterbi Decoders," Proc. VLSI '89, Munich, Germany, Sept. 1989, pp. 379-88.
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  • 9
    • 0031169619 scopus 로고    scopus 로고
    • A 1-Gb/s Four-State Sliding Block Viterbi Decoder
    • June
    • P. Black and T. Meng, " A 1-Gb/s Four-State Sliding Block Viterbi Decoder," IEEE JSSC, vol. 32, no 6, June 1997, pp. 797-805.
    • (1997) IEEE JSSC , vol.32 , Issue.6 , pp. 797-805
    • Black, P.1    Meng, T.2
  • 10
    • 0029343574 scopus 로고    scopus 로고
    • A 40 Mb/s Soft-Output Viterbi Decoder
    • July
    • O. J. Joeressen and H Meyr," A 40 Mb/s Soft-Output Viterbi Decoder," IEEE JSSC, vol 30, no 7, July 1997, pp. 812-18.
    • (1997) IEEE JSSC , vol.30 , Issue.7 , pp. 812-818
    • Joeressen, O.J.1    Meyr, H.2
  • 11
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    • A 40 MHz Encoder-Decoder Chip Generated by a Reed-Soiomon Code Compiler
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    • (1990) Proc. 1990 IEEE Custom Integrated Circuits Conf.
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  • 13
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    • A Fast Single-Chip Implementation of 8192 Complex Point FFT
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  • 14
  • 15
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    • Optimal Pipelined FFT Processing Based on Embedded Static RAM
    • San Diego, CA, Sept. 14-17
    • R. Makowitz and M. Mayr, "Optimal Pipelined FFT Processing Based on Embedded Static RAM," Proc. 8th Int'l. Conf. Sig. Processing Apps. and Tech., San Diego, CA, Sept. 14-17, 1997, pp. 157-61.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.