CPR: A configuration profiling tool

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1999, Pages 104-113

  Cadambi, Srihari ^a   Goldstein, Seth Copen ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; DATA FLOW ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS; GRAPH THEORY; OPTIMIZATION;

CONFIGURATION PROFILING TOOL; MACROGENERATOR LIBRARIES; SUBGRAPH MATCHING;

PROGRAM COMPILERS;

EID: 0033488512     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Jim Blinn. Fugue for MMX. IEEE Computer Graphics and Applications, pages 88-93, March-April 1997.
2. Mihai-Dan Budiu and Seth Copen Goldstein. Fast compilation for pipelined reconfigurable fabrics. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 1999. to be published.
3. Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, and Don Thomas. Managing pipeline-reconfigurable fpgas. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 55-64, Monterey, CA, February 1998.
4. Timothy J. Callahan, Philip Chong, Andre DeHon, and John Wawrzynek. Fast module mapping and placement for datapaths in fpgas. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 123-132, Monterey, CA, February 1998.
5. Sanjaya Kumar et al. Timimg sensitivity stressmark. Technical Report CDRL A001, Honeywell, Inc., January 1997. http://www.htc@honeywell.com/projects/.
6. S.C. Goldstein, H. Schmit, M. Bidui, M. Moe, S. Cadambi, R. Taylor, and R. Laufer. Piperench: A coprocessor for streaming multimedia acceleration. In International Symposium for Computer Architecture, Atlanta, GA, June 1999. to be published.
7. Xilinx Inc. Advanced carry logic techniques. XCELL, pages 42-44, Second Quarter 1996. http://www.xilinx.com/xcell/xcell21.htm.
8. Tai Ly, Knapp D., Miller R., and MacMillen, D. Scheduling using behavioral templates. In Proceedings of the 32nd Design Automation Conference, San Francisco, CA, June 1995.
9. Corazao M.R., Khalaf M.A., Guerra L.M., Potkonjak M., and Rabaey J.M. Performance optimization using template mapping for datapath intensive high-level synthesis. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 8, pages 877-888, August 1996.
10. David A. Patterson and John L. Hennessy. Computer Architecture A Quantitative Approach, Second Edition. Morgan Kaufmann Publishers, San Francisco, CA 94104, 1996.
11. J. Villasenor, B. Schoner, K. Chia, and C. Zapata. Configurable computing solutions for automatic target recognition. In J. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 70-79, Napa, CA, April 1996.
12. Kang Yi, Seong Yong Ohm, and Chu Shik John. An efficient fpga technology mapping tightly coupled with logic minimization. In IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E80-A, No.10, October 1997.