Automatic verification of safety and liveness for XScale-like processor models using WEB refinements

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 168-173

  Manolios, Panagiotis ^a   Srinivasan, Sudarshan K ^b  

^a Georgia Institute of Technology   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INSTRUCTION SETS; REFINEMENT; VERIFICATION; AUTOMATIC VERIFICATION; BRANCH PREDICTION; INSTRUCTION SET ARCHITECTURE; LIVENESS PROPERTIES; OUT-OF-ORDER COMPLETION; PIPELINED MACHINES; PROOF OBLIGATIONS; UNINTERPRETED FUNCTIONS;

AUTOMATION; FORMAL LOGIC; PROGRAM PROCESSORS; THEOREM PROVING; WORLD WIDE WEB; COMPUTER ARCHITECTURE; EXHIBITIONS;

COMPUTER SCIENCE; BOOLEAN ALGEBRA;

EID: 3042511935     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268844     Document Type: Conference Paper

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