A channel based asynchronous low power high performance standard-cell based sequential decoder implemented with QDI templates

Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 10, Issue , 2004, Pages 187-197

  Ozdag, Recep O ^a   Beerel, Peter A ^a  

^a University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DATA REDUCTION; SHIFT REGISTERS; SIGNAL TO NOISE RATIO; STANDARDS;

ASYNCHRONOUS DESIGNS; DECODERS; SYNCHRONOUS DESIGN;

DECODING;

EID: 2942648449     PISSN: 15228681     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

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