A new approach to analyze a sub-micron CMOS inverter

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 116-121

  Pattanaik, Manisha ^a   Banerjee, Swapna ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Analytical models; Circuit simulation; CMOS logic circuits; CMOS technology; Degradation; Inverters; MOSFETs; Particle scattering; Propagation delay; Semiconductor device modeling

Indexed keywords

ANALYTICAL MODELS; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; DEGRADATION; DELAY CIRCUITS; DESIGN; ELECTRIC INVERTERS; ELECTRIC NETWORK ANALYSIS; EMBEDDED SOFTWARE; MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICES; SYSTEMS ANALYSIS; VLSI CIRCUITS;

CMOS LOGIC CIRCUITS; CMOS TECHNOLOGY; MOSFETS; PARTICLE SCATTERING; PROPAGATION DELAYS;

EMBEDDED SYSTEMS;

EID: 2342448128     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183124     Document Type: Conference Paper

References (8)

1. Anas A. Hamoui, and Nicholas C. Rumin, "An analytical model for current, delay and power analysis of sub micron CMOS logic circuits", IEEE Trans on Circuits and Systems-II, October 2000, vol. 47, no. 10, pp. 999-1007.
2. Y. Cheng, M. C. Jeng, Z. Liu, J. Huang, M. Chan, K.Chen, P. K Ko, and C. Hu, "A physical and scalable I-V model in BSIM3v3 for analog and Digital circuit simulation," IEEE Trans. Electron Devices, Feb. 1997, vol.44, pp. 277-286.
3. Yutao Ma et al., "Analytical charge-control and I-V model for sub micrometer deep sub micrometer MOSFETs comprising quantum mechanically effect", IEEE Trans. Computer Aided-Design, April 2001,vol. 20, no.4.
4. A. Schwarz and S. E. Russek, "Semi-empirical equations for electron velocity in silicon: part II- MOS inversion layer," IEEE Trans. Electron Devices, December 1983, vol. 30, no.12, pp. 1639.
5. Akira Hiroki, Shinji odanaka, Kikuyo Ohe and Hideya Esaki, "A mobility model for sub-micrometer MOSFET simulations including hot-carrier induced device degradation", IEEE Trans.Electron devices, September 1988, vol. 35, no. 9.
6. Y. Cheng et al., "BSIM3v3 manual", Univ California, Berkeley, 1997-1998.
7. X. Zhou, K. Y. Lim, "A general approach to compact threshold voltage formulation based on 2-D numerical simulation and experimental correlation for deep sub-micron ULSI technology development," IEEE Trans. Electron Devices, Jan. 2000,vol. 47, pp.214-221.
8. Xing Zhou et al., "Unified MOSFET compact I-V model formulation through physics-base effective transformation", IEEE Trans. Electron Devices, May 2001, vol. 48, no. 5.