Estimating detection probability of interconnect opens using stuck-at tests

Proceedings of the ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2004, Pages 254-259

  Ghosh, Shalini ^a   Ferguson, F Joel ^a  

^a University of California Santa Cruz   (United States)

Author keywords

Break fault; Interconnect open; Stuck at test

Indexed keywords

ALGORITHMS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC WIRING; LOGIC GATES; PROBABILITY; TRANSISTORS;

INTERCONNECT WIRING; PARAMETRIC DELAY DEFECTS;

INTERCONNECTION NETWORKS;

EID: 2942670023     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/988952.989014     Document Type: Conference Paper

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